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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/09/30 17:33:58 simont
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// prepared header
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_tb;
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module oc8051_tb;
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reg rst, clk, ea;
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reg rst, clk;
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reg [15:0] pc_in;
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reg [15:0] pc_in;
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reg [7:0] p0_in, p1_in, p2_in, op1, op2, op3;
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reg [7:0] p0_in, p1_in, p2_in;
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wire [15:0] ext_addr, rom_addr;
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wire [31:0] idat_i;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i, ack_xram, ack_uart, cyc_o;
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wire [15:0] ext_addr, iadr_o;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i, ack_xram, ack_uart, cyc_o, iack_i, istb_o, icyc_o;
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wire [7:0] data_in, data_out, p0_out, p1_out, p2_out, p3_out, data_out_uart, data_out_xram, p3_in;
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wire [7:0] data_in, data_out, p0_out, p1_out, p2_out, p3_out, data_out_uart, data_out_xram, p3_in;
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///
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///
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/// buffer for test vectors
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/// buffer for test vectors
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///
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///
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//
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//
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// buffer
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// buffer
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reg [23:0] buff [255:0];
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reg [23:0] buff [255:0];
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reg ea [1:0];
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integer num;
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integer num;
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oc8051_top oc8051_top_1(.rst(rst), .clk(clk), .int0(int0), .int1(int1),
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oc8051_top oc8051_top_1(.rst(rst), .clk(clk), .int0(int0), .int1(int1),
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.dat_i(data_in), .dat_o(data_out),
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.dat_i(data_in), .dat_o(data_out),
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.adr_o(ext_addr), .rom_addr(rom_addr), .we_o(write), .p0_in(p0_in),
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.adr_o(ext_addr), .iadr_o(iadr_o), .istb_o(istb_o), .iack_i(iack_i),
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.icyc_o(icyc_o), .we_o(write), .p0_in(p0_in),
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.ack_i(ack_i), .stb_o(stb_o), .cyc_o(cyc_o),
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.ack_i(ack_i), .stb_o(stb_o), .cyc_o(cyc_o),
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.p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in), .p0_out(p0_out), .p1_out(p1_out),
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.p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in), .p0_out(p0_out), .p1_out(p1_out),
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.p2_out(p2_out), .p3_out(p3_out), .op1(op1), .op2(op2), .op3(op3), .ea(ea),
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.p2_out(p2_out), .p3_out(p3_out), .idat_i(idat_i), .ea(ea[0]),
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.rxd(rxd), .txd(txd), .t0(t0), .t1(t1));
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.rxd(rxd), .txd(txd), .t0(t0), .t1(t1));
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oc8051_xram oc8051_xram1 (.clk(clk), .wr(write_xram), .addr(ext_addr), .data_in(data_out), .data_out(data_out_xram), .ack(ack_xram), .stb(stb_o));
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oc8051_xram oc8051_xram1 (.clk(clk), .rst(rst), .wr(write_xram), .addr(ext_addr), .data_in(data_out), .data_out(data_out_xram), .ack(ack_xram), .stb(stb_o));
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
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.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
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assign write_xram = p3_out[7] & write;
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assign write_xram = p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign ack_i = p3_out[7] ? ack_xram : ack_uart;
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assign ack_i = p3_out[7] ? ack_xram : ack_uart;
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Line 107... |
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initial begin
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initial begin
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clk= 1'b0;
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clk= 1'b0;
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rst= 1'b1;
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rst= 1'b1;
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// int0= 1'b1;
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// int1= 1'b1;
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pc_in = 16'h0000;
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pc_in = 16'h0000;
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p0_in = 8'h00;
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p0_in = 8'h00;
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p1_in = 8'h00;
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p1_in = 8'h00;
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p2_in = 8'h00;
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p2_in = 8'h00;
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op1 = 8'h00;
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op2 = 8'h00;
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op3 = 8'h00;
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ea =1'b1;
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#22
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#22
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rst = 1'b0;
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rst = 1'b0;
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//#2000000
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//#2000000
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#4444000
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//#4444000
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//#500000
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#7000000
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$display("time ",$time, "\n faulire: end of time\n \n");
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$display("time ",$time, "\n faulire: end of time\n \n");
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$finish;
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$finish;
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end
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end
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/*initial begin
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#222
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int= 1'b1;
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int_v= 8'h50;
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#20
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int= 1'b0;
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end*/
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always clk = #5 ~clk;
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always clk = #5 ~clk;
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initial
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initial
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$readmemh("../src/oc8051_test.vec", buff);
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$readmemh("../../../asm/vec/oc8051_test.vec", buff);
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initial
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$readmemb("../oc8051_ea.in", ea);
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initial num= 0;
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initial num= 0;
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always @(p0_out or p1_out or p2_out)
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always @(p0_out or p1_out or p2_out)
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begin
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begin
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