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[/] [8051/] [trunk/] [bench/] [verilog/] [oc8051_xrom.v] - Diff between revs 97 and 157

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Rev 97	Rev 157
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2003/04/02 11:38:40 simont`
	`// initial inport`
	`//`
`// Revision 1.1 2002/10/17 18:56:13 simont`	`// Revision 1.1 2002/10/17 18:56:13 simont`
`// initial CVS input`	`// initial CVS input`
`//`	`//`
`//`	`//`

Line 57...	Line 60...
`input rst, clk, stb_i, cyc_i;`	`input rst, clk, stb_i, cyc_i;`
`input [15:0] addr;`	`input [15:0] addr;`
`output ack_o;`	`output ack_o;`
`output [31:0] data;`	`output [31:0] data;`


`reg ack_o;`	`reg ack_o;`
`reg [31:0] data;`	`reg [31:0] data;`

`reg [7:0] buff [0:65535];`	`reg [7:0] buff [0:65535];`
`//reg [7:0] buff [8388607:0];`	`//reg [7:0] buff [8388607:0];`
`reg [2:0] cnt;`	`reg [2:0] cnt;`
`integer i;`	`integer i;`

Line 78...	Line 83...
`begin`	`begin`
`if (rst) begin`	`if (rst) begin`
`data <= #1 31'h0;`	`data <= #1 31'h0;`
`ack_o <= #1 1'b0;`	`ack_o <= #1 1'b0;`
`end else if (stb_i && ((DELAY==3'b000) \|\| (cnt==3'b000))) begin`	`end else if (stb_i && ((DELAY==3'b000) \|\| (cnt==3'b000))) begin`
`data <= #1 {buff [addr], buff[addr+1], buff[addr+2], buff[addr+3]};`	`data <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};`
`ack_o <= #1 1'b1;`	`ack_o <= #1 1'b1;`
`end else`	`end else`
`ack_o <= #1 1'b0;`	`ack_o <= #1 1'b0;`
`end`	`end`

Line 95...	Line 100...
`else if (stb_i)`	`else if (stb_i)`
`cnt <= #1 cnt - 3'b001;`	`cnt <= #1 cnt - 3'b001;`
`else cnt <= #1 DELAY;`	`else cnt <= #1 DELAY;`
`end`	`end`


`endmodule`	`endmodule`



`No newline at end of file`	`No newline at end of file`

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[/] [8051/] [trunk/] [bench/] [verilog/] [oc8051_xrom.v] - Diff between revs 97 and 157