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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, des2_r, desCy, desAc, desOv);
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module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, desCy, desAc, desOv);
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//
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//
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// op_code (in) operation code [oc8051_decoder.alu_op -r]
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// op_code (in) operation code [oc8051_decoder.alu_op -r]
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// src1 (in) first operand [oc8051_alu_src1_sel.des]
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// src1 (in) first operand [oc8051_alu_src1_sel.des]
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// src2 (in) second operand [oc8051_alu_src2_sel.des]
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// src2 (in) second operand [oc8051_alu_src2_sel.des]
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// src3 (in) third operand [oc8051_alu_src3_sel.des]
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// src3 (in) third operand [oc8051_alu_src3_sel.des]
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// srcAc (in) auxiliary carry input [oc8051_psw.data_out[6] ]
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// srcAc (in) auxiliary carry input [oc8051_psw.data_out[6] ]
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// bit_in (in) bit input, used for logic operatins on bits [oc8051_ram_sel.bit_out]
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// bit_in (in) bit input, used for logic operatins on bits [oc8051_ram_sel.bit_out]
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// des1 (out)
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// des1 (out)
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// des1_r (out)
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// des1_r (out)
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// des2 (out)
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// des2 (out)
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// des2_r (out)
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// desCy (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
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// desCy (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
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// desAc (out) auxiliary carry output [oc8051_psw.ac_in]
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// desAc (out) auxiliary carry output [oc8051_psw.ac_in]
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// desOv (out) Overflow output [oc8051_psw.ov_in]
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// desOv (out) Overflow output [oc8051_psw.ov_in]
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//
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//
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input srcCy, srcAc, bit_in, clk, rst; input [3:0] op_code; input [7:0] src1, src2, src3;
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input srcCy, srcAc, bit_in, clk, rst; input [3:0] op_code; input [7:0] src1, src2, src3;
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output desCy, desAc, desOv;
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output desCy, desAc, desOv;
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output [7:0] des1, des2;
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output [7:0] des1, des2;
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output [7:0] des1_r, des2_r;
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output [7:0] des1_r;
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reg desCy, desAc, desOv;
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reg desCy, desAc, desOv;
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reg [7:0] des1, des2;
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reg [7:0] des1, des2;
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reg [7:0] des1_r, des2_r;
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reg [7:0] des1_r;
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//
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//
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//add
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//add
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//
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//
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wire [4:0] add1, add2, add3, add4;
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wire [4:0] add1, add2, add3, add4;
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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des1_r <= #1 8'h0;
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des1_r <= #1 8'h0;
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des2_r <= #1 8'h0;
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end else begin
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end else begin
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des1_r <= #1 des1;
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des1_r <= #1 des1;
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des2_r <= #1 des2;
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end
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end
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endmodule
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endmodule
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