URL
https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu.v] - Diff between revs 11 and 22
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 11 |
Rev 22 |
| Line 177... |
Line 177... |
enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
//operation multiply
|
//operation multiply
|
`OC8051_ALU_MUL: begin
|
`OC8051_ALU_MUL: begin
|
des1 = mulsrc2;
|
des1 = mulsrc1;
|
des2 = mulsrc1;
|
des2 = mulsrc2;
|
desOv = mulOv;
|
desOv = mulOv;
|
desCy = 1'b0;
|
desCy = 1'b0;
|
desAc = 1'bx;
|
desAc = 1'bx;
|
enable_mul = 1'b1;
|
enable_mul = 1'b1;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
//operation divide
|
//operation divide
|
`OC8051_ALU_DIV: begin
|
`OC8051_ALU_DIV: begin
|
des1 = divsrc2;
|
des1 = divsrc1;
|
des2 = divsrc1;
|
des2 = divsrc2;
|
desOv = divOv;
|
desOv = divOv;
|
desAc = 1'bx;
|
desAc = 1'bx;
|
desCy = 1'b0;
|
desCy = 1'b0;
|
enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b1;
|
enable_div = 1'b1;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
