URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu.v] - Diff between revs 7 and 8

Rev 7	Rev 8
Line 52...	Line 52...

`include "oc8051_defines.v"	`include "oc8051_defines.v"



`module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, desCy, desAc, desOv);`	`module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, des2_r, desCy, desAc, desOv);`
`//`	`//`
`// op_code (in) operation code [oc8051_decoder.alu_op -r]`	`// op_code (in) operation code [oc8051_decoder.alu_op -r]`
`// src1 (in) first operand [oc8051_alu_src1_sel.des]`	`// src1 (in) first operand [oc8051_alu_src1_sel.des]`
`// src2 (in) second operand [oc8051_alu_src2_sel.des]`	`// src2 (in) second operand [oc8051_alu_src2_sel.des]`
`// src3 (in) third operand [oc8051_alu_src3_sel.des]`	`// src3 (in) third operand [oc8051_alu_src3_sel.des]`
Line 352...	Line 352...
`endcase`	`endcase`
`end`	`end`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst) begin`	`if (rst) begin`
`dst1_r <= #1 8'h0;`	`des1_r <= #1 8'h0;`
`dst2_r <= #1 8'h0;`	`des2_r <= #1 8'h0;`
`else begin`	`end else begin`
`dst1_r <= #1 dst1;`	`des1_r <= #1 des1;`
`dst2_r <= #1 dst2;`	`des2_r <= #1 des2;`
`end`	`end`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`