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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_b_register.v] - Diff between revs 116 and 118

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Rev 116	Rev 118
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.8 2003/04/07 14:58:02 simont`
	`// change sfr's interface.`
	`//`
`// Revision 1.7 2003/01/13 14:14:40 simont`	`// Revision 1.7 2003/01/13 14:14:40 simont`
`// replace some modules`	`// replace some modules`
`//`	`//`
`// Revision 1.6 2002/09/30 17:33:59 simont`	`// Revision 1.6 2002/09/30 17:33:59 simont`
`// prepared header`	`// prepared header`
Line 58...	Line 61...

`include "oc8051_defines.v"	`include "oc8051_defines.v"


`module oc8051_b_register (clk, rst, bit_in, data_in, wr, wr_bit,`	`module oc8051_b_register (clk, rst, bit_in, data_in, wr, wr_bit,`
`wr_addr, data_out, wr_sfr);`	`wr_addr, data_out);`


`input clk, rst, wr, wr_bit, bit_in;`	`input clk, rst, wr, wr_bit, bit_in;`
`input [2:0] wr_sfr;`
`input [7:0] wr_addr, data_in;`	`input [7:0] wr_addr, data_in;`

`output [7:0] data_out;`	`output [7:0] data_out;`

`reg [7:0] data_out;`	`reg [7:0] data_out;`
Line 76...	Line 78...
`//must check if write high and correct address`	`//must check if write high and correct address`
`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`begin`	`begin`
`if (rst)`	`if (rst)`
data_out <= #1 `OC8051_RST_B;	data_out <= #1 `OC8051_RST_B;
else if (wr_sfr==`OC8051_WRS_BA)
`data_out <= #1 data_in;`
`else if (wr) begin`	`else if (wr) begin`
`if (!wr_bit) begin`	`if (!wr_bit) begin`
if (wr_addr==`OC8051_SFR_B)	if (wr_addr==`OC8051_SFR_B)
`data_out <= #1 data_in;`	`data_out <= #1 data_in;`
`end else begin`	`end else begin`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_b_register.v] - Diff between revs 116 and 118