| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.6 2002/09/30 17:33:59 simont
|
|
// prepared header
|
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "oc8051_timescale.v"
|
`include "oc8051_timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
`include "oc8051_defines.v"
|
`include "oc8051_defines.v"
|
|
|
|
|
module oc8051_b_register (clk, rst, bit_in, bit_out, data_in, wr, wr_bit, wr_addr, rd_addr, data_out);
|
module oc8051_b_register (clk, rst, bit_in, bit_out, data_in, wr, wr_bit,
|
|
wr_addr, rd_addr, data_out, wr_sfr);
|
//
|
//
|
// clk (in) clock
|
// clk (in) clock
|
// rst (in) reset
|
// rst (in) reset
|
// bit_in (in) bit input - used in case of writing bits to b register (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
|
// bit_in (in) bit input - used in case of writing bits to b register (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
|
// data_in (in) data input - used to write to b register [oc8051_alu.des1]
|
// data_in (in) data input - used to write to b register [oc8051_alu.des1]
|
// wr (in) write - actine high [oc8051_decoder.wr -r]
|
// wr (in) write - actine high [oc8051_decoder.wr -r]
|
// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
|
// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
|
// wr_addr (in) write address [oc8051_ram_wr_sel.out]
|
// wr_addr (in) write address [oc8051_ram_wr_sel.out]
|
// data_out (out) data output [oc8051_ram_sel.b_reg]
|
// data_out (out) data output [oc8051_ram_sel.b_reg]
|
|
// wr_sfr
|
//
|
//
|
|
|
|
|
input clk, rst, wr, wr_bit, bit_in;
|
input clk, rst, wr, wr_bit, bit_in;
|
input [2:0] rd_addr;
|
input [2:0] rd_addr, wr_sfr;
|
input [7:0] wr_addr, data_in;
|
input [7:0] wr_addr, data_in;
|
|
|
output bit_out;
|
output bit_out;
|
output [7:0] data_out;
|
output [7:0] data_out;
|
|
|
| Line 81... |
Line 86... |
//must check if write high and correct address
|
//must check if write high and correct address
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
data_out <= #1 `OC8051_RST_B;
|
data_out <= #1 `OC8051_RST_B;
|
|
else if (wr_sfr==`OC8051_WRS_BA)
|
|
data_out <= #1 data_in;
|
else if (wr) begin
|
else if (wr) begin
|
if (!wr_bit) begin
|
if (!wr_bit) begin
|
if (wr_addr==`OC8051_SFR_B)
|
if (wr_addr==`OC8051_SFR_B)
|
data_out <= #1 data_in;
|
data_out <= #1 data_in;
|
end else begin
|
end else begin
|
