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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_decoder.v] - Diff between revs 54 and 62

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Line 43... Line 43...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.12  2002/10/17 18:50:00  simont
 
// cahnge interface to instruction rom
 
//
// Revision 1.11  2002/09/30 17:33:59  simont
// Revision 1.11  2002/09/30 17:33:59  simont
// prepared header
// prepared header
//
//
//
//
 
 
Line 59... Line 62...
 
 
 
 
module oc8051_decoder (clk, rst, op_in, eq, ram_rd_sel, ram_wr_sel, bit_addr,
module oc8051_decoder (clk, rst, op_in, eq, ram_rd_sel, ram_wr_sel, bit_addr,
wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr,
wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr,
pc_sel, comp_sel, rom_addr_sel, ext_addr_sel, wad2, rd, we_o, reti,
pc_sel, comp_sel, rom_addr_sel, ext_addr_sel, wad2, rd, we_o, reti,
rmw, stb_o, ack_i, wr_xaddr, istb, ea, iack);
rmw, stb_o, ack_i, wr_xaddr, istb, ea, iack, pc_wait, nop);
 
 
//
//
// clk          (in)  clock
// clk          (in)  clock
// rst          (in)  reset
// rst          (in)  reset
// op_in        (in)  operation code [oc8051_op_select.op1]
// op_in        (in)  operation code [oc8051_op_select.op1]
Line 90... Line 93...
// reti         (out) return from interrupt [pin]
// reti         (out) return from interrupt [pin]
// rmw          (out) read modify write feature [oc8051_ports.rmw]
// rmw          (out) read modify write feature [oc8051_ports.rmw]
// istb         (out) strobe to instruction rom
// istb         (out) strobe to instruction rom
// ea           (in)  extrnal access
// ea           (in)  extrnal access
// iack         (in)  scknowlage from external rom
// iack         (in)  scknowlage from external rom
 
// pc_wait      (out)
 
// nop          (out) insert nops
//
//
 
 
input clk, rst, eq, ack_i, iack, ea;
input clk, rst, eq, ack_i, iack, ea;
input [7:0] op_in;
input [7:0] op_in;
 
 
output wr, reti, we_o, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
output wr, reti, we_o, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
pc_wr, wad2, rmw, stb_o, wr_xaddr, istb;
pc_wr, wad2, rmw, stb_o, wr_xaddr, istb, pc_wait;
output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
output [2:0] ram_wr_sel, imm_sel;
output [2:0] ram_wr_sel, imm_sel;
output [3:0] alu_op;
output [3:0] alu_op;
output rd;
output rd, nop;
 
 
reg reti, write_x, rmw, stb_buff, we_buff, istb_t;
reg reti, write_x, rmw, stb_buff, we_buff, istb_t;
reg wr,  bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2, stb, stbw, wr_xaddr;
reg wr,  bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2, stb, stbw, wr_xaddr;
reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel;
reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel;
reg [3:0] alu_op;
reg [3:0] alu_op;
Line 113... Line 118...
//
//
// state        if 2'b00 then normal execution, sle instructin that need more than one clock
// state        if 2'b00 then normal execution, sle instructin that need more than one clock
// op           instruction buffer
// op           instruction buffer
reg [1:0] state;
reg [1:0] state;
reg [7:0] op;
reg [7:0] op;
 
reg stb_i;
 
wire [7:0] op_cur;
 
 
//
//
// if state = 2'b00 then read nex instruction
// if state = 2'b00 then read nex instruction
assign rd = !state[0] && !state[1] && !stb_o;
assign rd = !state[0] && !state[1] && !stb_o;
 
 
assign istb = (!state[1]) || istb_t;
assign istb = ((!state[1]) && stb_i) || istb_t;
 
assign nop = (!state[1]) || istb_t;
 
 
 
 
assign stb_o = stb_buff || stbw;
assign stb_o = stb_buff || stbw;
assign we_o = we_buff;
assign we_o = we_buff;
//assign we_o = write_x || we_buff;
//assign we_o = write_x || we_buff;
 
 
 
assign op_cur = (state[0] || state[1] || stb_o) ? op : op_in;
 
 
 
assign pc_wait = !istb_t && rd;
 
 
//
//
// main block
// main block
// case of instruction set control signals
// case of instruction set control signals
always @(op_in or eq or state or op or stb_o or istb_t)
always @(op_cur or eq or state or op or stb_o or istb_t)
begin
begin
  if (stb_o) begin
  if (stb_o) begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
Line 143... Line 156...
          cy_sel = `OC8051_CY_0;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;
 
          stb_i = 1'b1;
 
          bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
  end else begin
  end else begin
    case (state)
    case (state)
      2'b01: begin
      2'b01: begin
    casex (op)
    casex (op_cur)
      `OC8051_ACALL :begin
      `OC8051_ACALL :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_SP;
          ram_wr_sel = `OC8051_RWS_SP;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
Line 166... Line 181...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;
          rmw = `OC8051_RMW_N;
 
          stb_i = 1'b1;
          bit_addr = 1'b0;
          bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
Line 189... Line 205...
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;
          rmw = `OC8051_RMW_N;
          bit_addr = 1'b0;
          bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 211... Line 228...
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;
          rmw = `OC8051_RMW_N;
          bit_addr = 1'b0;
          bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
      `OC8051_MOVC_DP :begin
 
          ram_rd_sel = `OC8051_RRS_DC;
 
          ram_wr_sel = `OC8051_RWS_ACC;
 
          src_sel1 = `OC8051_ASS_IMM;
 
          src_sel2 = `OC8051_ASS_DC;
 
          alu_op = `OC8051_ALU_NOP;
 
          wr = 1'b1;
 
          psw_set = `OC8051_PS_NOT;
 
          cy_sel = `OC8051_CY_0;
 
          pc_wr = `OC8051_PCW_N;
 
          pc_sel = `OC8051_PIS_DC;
 
          imm_sel = `OC8051_IDS_OP1;
 
          src_sel3 = `OC8051_AS3_DP;
 
          comp_sel = `OC8051_CSS_DC;
 
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          wad2 = `OC8051_WAD_N;
 
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
 
        end
 
      `OC8051_MOVC_PC :begin
 
          ram_rd_sel = `OC8051_RRS_DC;
 
          ram_wr_sel = `OC8051_RWS_ACC;
 
          src_sel1 = `OC8051_ASS_IMM;
 
          src_sel2 = `OC8051_ASS_DC;
 
          alu_op = `OC8051_ALU_NOP;
 
          wr = 1'b1;
 
          psw_set = `OC8051_PS_NOT;
 
          cy_sel = `OC8051_CY_0;
 
          pc_wr = `OC8051_PCW_N;
 
          pc_sel = `OC8051_PIS_DC;
 
          imm_sel = `OC8051_IDS_OP1;
 
          src_sel3 = `OC8051_AS3_PC;
 
          comp_sel = `OC8051_CSS_DC;
 
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          wad2 = `OC8051_WAD_N;
 
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
        end
 
      `OC8051_DIV : begin
      `OC8051_DIV : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel2 = `OC8051_ASS_RAM;
          src_sel2 = `OC8051_ASS_RAM;
Line 269... Line 248...
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
 
          stb_i = 1'b1;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
Line 289... Line 269...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      default begin
      default begin
Line 308... Line 289...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
      end
      end
    endcase
    endcase
    end
    end
    2'b10:
    2'b10:
    casex (op)
    casex (op_cur)
      `OC8051_CJNE_R : begin
      `OC8051_CJNE_R : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
Line 332... Line 314...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 352... Line 335...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 372... Line 356...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 392... Line 377...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 412... Line 398...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 432... Line 419...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 452... Line 440...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 472... Line 461...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 492... Line 482...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_CY;
          comp_sel = `OC8051_CSS_CY;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 512... Line 503...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 532... Line 524...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 552... Line 545...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_CY;
          comp_sel = `OC8051_CSS_CY;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 572... Line 566...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_AZ;
          comp_sel = `OC8051_CSS_AZ;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
Line 592... Line 587...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_AZ;
          comp_sel = `OC8051_CSS_AZ;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
      `OC8051_MOVC_DP :begin
      `OC8051_MOVC_DP :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          wr = 1'b1;
          psw_set = `OC8051_PS_NOT;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_OP1;
          src_sel3 = `OC8051_AS3_DP;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_DES;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
 
 
        end
        end
      `OC8051_MOVC_PC :begin
      `OC8051_MOVC_PC :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          wr = 1'b1;
          psw_set = `OC8051_PS_NOT;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_OP1;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_DES;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_SJMP : begin
      `OC8051_SJMP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
Line 651... Line 649...
          pc_sel = `OC8051_PIS_ALU;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DIV : begin
      `OC8051_DIV : begin
Line 670... Line 669...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MUL : begin
      `OC8051_MUL : begin
Line 690... Line 690...
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
 
          stb_i = 1'b1;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      default begin
      default begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
Line 708... Line 709...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
      end
      end
    endcase
    endcase
 
 
    2'b11:
    2'b11:
    casex (op)
    casex (op_cur)
 
      `OC8051_MOVC_DP :begin
 
          ram_rd_sel = `OC8051_RRS_DC;
 
          ram_wr_sel = `OC8051_RWS_DC;
 
          src_sel1 = `OC8051_ASS_DC;
 
          src_sel2 = `OC8051_ASS_DC;
 
          alu_op = `OC8051_ALU_NOP;
 
          wr = 1'b0;
 
          psw_set = `OC8051_PS_NOT;
 
          cy_sel = `OC8051_CY_0;
 
          pc_wr = `OC8051_PCW_N;
 
          pc_sel = `OC8051_PIS_DC;
 
          imm_sel = `OC8051_IDS_DC;
 
          src_sel3 = `OC8051_AS3_DP;
 
          comp_sel = `OC8051_CSS_DC;
 
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
 
          wad2 = `OC8051_WAD_N;
 
          rom_addr_sel = `OC8051_RAS_DES;
 
 
 
 
 
        end
 
      `OC8051_MOVC_PC :begin
 
          ram_rd_sel = `OC8051_RRS_DC;
 
          ram_wr_sel = `OC8051_RWS_DC;
 
          src_sel1 = `OC8051_ASS_DC;
 
          src_sel2 = `OC8051_ASS_DC;
 
          alu_op = `OC8051_ALU_NOP;
 
          wr = 1'b0;
 
          psw_set = `OC8051_PS_NOT;
 
          cy_sel = `OC8051_CY_0;
 
          pc_wr = `OC8051_PCW_N;
 
          pc_sel = `OC8051_PIS_DC;
 
          imm_sel = `OC8051_IDS_DC;
 
          src_sel3 = `OC8051_AS3_PC;
 
          comp_sel = `OC8051_CSS_DC;
 
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
 
          wad2 = `OC8051_WAD_N;
 
          rom_addr_sel = `OC8051_RAS_DES;
 
 
 
        end
      `OC8051_CJNE_R : begin
      `OC8051_CJNE_R : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_IMM;
Line 731... Line 774...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CJNE_I : begin
      `OC8051_CJNE_I : begin
Line 750... Line 794...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CJNE_D : begin
      `OC8051_CJNE_D : begin
Line 769... Line 814...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CJNE_C : begin
      `OC8051_CJNE_C : begin
Line 788... Line 834...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DJNZ_R : begin
      `OC8051_DJNZ_R : begin
Line 807... Line 854...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2_PCL;
          imm_sel = `OC8051_IDS_OP2_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DJNZ_D : begin
      `OC8051_DJNZ_D : begin
Line 826... Line 874...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_RET : begin
      `OC8051_RET : begin
Line 845... Line 894...
          pc_sel = `OC8051_PIS_SP;
          pc_sel = `OC8051_PIS_SP;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_RETI : begin
      `OC8051_RETI : begin
Line 864... Line 914...
          pc_sel = `OC8051_PIS_SP;
          pc_sel = `OC8051_PIS_SP;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DIV : begin
      `OC8051_DIV : begin
Line 883... Line 934...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MUL : begin
      `OC8051_MUL : begin
Line 902... Line 954...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
     default begin
     default begin
Line 921... Line 974...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
      end
      end
    endcase
    endcase
    default: begin
    default: begin
    casex (op_in)
    casex (op_cur)
      `OC8051_ACALL :begin
      `OC8051_ACALL :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_SP;
          ram_wr_sel = `OC8051_RWS_SP;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
Line 943... Line 997...
          pc_wr = `OC8051_PCW_Y;
          pc_wr = `OC8051_PCW_Y;
          pc_sel = `OC8051_PIS_I11;
          pc_sel = `OC8051_PIS_I11;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_AJMP : begin
      `OC8051_AJMP : begin
Line 962... Line 1017...
          pc_wr = `OC8051_PCW_Y;
          pc_wr = `OC8051_PCW_Y;
          pc_sel = `OC8051_PIS_I11;
          pc_sel = `OC8051_PIS_I11;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ADD_R : begin
      `OC8051_ADD_R : begin
Line 981... Line 1037...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ADDC_R : begin
      `OC8051_ADDC_R : begin
Line 1000... Line 1057...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ANL_R : begin
      `OC8051_ANL_R : begin
Line 1019... Line 1077...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CJNE_R : begin
      `OC8051_CJNE_R : begin
Line 1038... Line 1097...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DEC_R : begin
      `OC8051_DEC_R : begin
Line 1057... Line 1117...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DJNZ_R : begin
      `OC8051_DJNZ_R : begin
Line 1076... Line 1137...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_INC_R : begin
      `OC8051_INC_R : begin
Line 1095... Line 1157...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_R : begin
      `OC8051_MOV_R : begin
Line 1114... Line 1177...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
 
 
Line 1134... Line 1198...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_DR : begin
      `OC8051_MOV_DR : begin
Line 1153... Line 1218...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_CR : begin
      `OC8051_MOV_CR : begin
Line 1172... Line 1238...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_RD : begin
      `OC8051_MOV_RD : begin
Line 1191... Line 1258...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ORL_R : begin
      `OC8051_ORL_R : begin
Line 1210... Line 1278...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_SUBB_R : begin
      `OC8051_SUBB_R : begin
Line 1229... Line 1298...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_XCH_R : begin
      `OC8051_XCH_R : begin
Line 1248... Line 1318...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_XRL_R : begin
      `OC8051_XRL_R : begin
Line 1267... Line 1338...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
 
 
Line 1288... Line 1360...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ADDC_I : begin
      `OC8051_ADDC_I : begin
Line 1307... Line 1380...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ANL_I : begin
      `OC8051_ANL_I : begin
Line 1326... Line 1400...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CJNE_I : begin
      `OC8051_CJNE_I : begin
Line 1345... Line 1420...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DEC_I : begin
      `OC8051_DEC_I : begin
Line 1364... Line 1440...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_INC_I : begin
      `OC8051_INC_I : begin
Line 1383... Line 1460...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_I : begin
      `OC8051_MOV_I : begin
Line 1402... Line 1480...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_ID : begin
      `OC8051_MOV_ID : begin
Line 1421... Line 1500...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_AI : begin
      `OC8051_MOV_AI : begin
Line 1440... Line 1520...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_DI : begin
      `OC8051_MOV_DI : begin
Line 1459... Line 1540...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_CI : begin
      `OC8051_MOV_CI : begin
Line 1478... Line 1560...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOVX_IA : begin
      `OC8051_MOVX_IA : begin
Line 1497... Line 1580...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
        end
        end
      `OC8051_MOVX_AI :begin
      `OC8051_MOVX_AI :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
Line 1515... Line 1599...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
        end
        end
      `OC8051_ORL_I : begin
      `OC8051_ORL_I : begin
          ram_rd_sel = `OC8051_RRS_I;
          ram_rd_sel = `OC8051_RRS_I;
Line 1533... Line 1618...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_SUBB_I : begin
      `OC8051_SUBB_I : begin
Line 1552... Line 1638...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_XCH_I : begin
      `OC8051_XCH_I : begin
Line 1571... Line 1658...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_XCHD :begin
      `OC8051_XCHD :begin
Line 1590... Line 1678...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_XRL_I : begin
      `OC8051_XRL_I : begin
Line 1609... Line 1698...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
 
 
Line 1630... Line 1720...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ADD_C : begin
      `OC8051_ADD_C : begin
Line 1649... Line 1740...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ADDC_D : begin
      `OC8051_ADDC_D : begin
Line 1668... Line 1760...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ADDC_C : begin
      `OC8051_ADDC_C : begin
Line 1687... Line 1780...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ANL_D : begin
      `OC8051_ANL_D : begin
Line 1706... Line 1800...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ANL_C : begin
      `OC8051_ANL_C : begin
Line 1725... Line 1820...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ANL_DD : begin
      `OC8051_ANL_DD : begin
Line 1744... Line 1840...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ANL_DC : begin
      `OC8051_ANL_DC : begin
Line 1763... Line 1860...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3;
          imm_sel = `OC8051_IDS_OP3;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ANL_B : begin
      `OC8051_ANL_B : begin
Line 1782... Line 1880...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ANL_NB : begin
      `OC8051_ANL_NB : begin
Line 1801... Line 1900...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CJNE_D : begin
      `OC8051_CJNE_D : begin
Line 1820... Line 1920...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CJNE_C : begin
      `OC8051_CJNE_C : begin
Line 1839... Line 1940...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CLR_A : begin
      `OC8051_CLR_A : begin
Line 1858... Line 1960...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CLR_C : begin
      `OC8051_CLR_C : begin
Line 1877... Line 1980...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CLR_B : begin
      `OC8051_CLR_B : begin
Line 1896... Line 2000...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CPL_A : begin
      `OC8051_CPL_A : begin
Line 1915... Line 2020...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3;   ///****
          imm_sel = `OC8051_IDS_OP3;   ///****
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CPL_C : begin
      `OC8051_CPL_C : begin
Line 1934... Line 2040...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3;  ///*****
          imm_sel = `OC8051_IDS_OP3;  ///*****
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_CPL_B : begin
      `OC8051_CPL_B : begin
Line 1950... Line 2057...
          psw_set = `OC8051_PS_NOT;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_RAM;
          cy_sel = `OC8051_CY_RAM;
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3;  ///***
          imm_sel = `OC8051_IDS_OP3;  ///***
 
          stb_i = 1'b1;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
Line 1972... Line 2080...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DEC_A : begin
      `OC8051_DEC_A : begin
Line 1991... Line 2100...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DEC_D : begin
      `OC8051_DEC_D : begin
Line 2010... Line 2120...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DIV : begin
      `OC8051_DIV : begin
Line 2029... Line 2140...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_DJNZ_D : begin
      `OC8051_DJNZ_D : begin
Line 2048... Line 2160...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_INC_A : begin
      `OC8051_INC_A : begin
Line 2067... Line 2180...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_INC_D : begin
      `OC8051_INC_D : begin
Line 2086... Line 2200...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_INC_DP : begin
      `OC8051_INC_DP : begin
Line 2105... Line 2220...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DP;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_JB : begin
      `OC8051_JB : begin
Line 2124... Line 2240...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_JBC :begin
      `OC8051_JBC :begin
Line 2143... Line 2260...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_JC : begin
      `OC8051_JC : begin
Line 2162... Line 2280...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2_PCL;
          imm_sel = `OC8051_IDS_OP2_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_CY;
          comp_sel = `OC8051_CSS_CY;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_JMP : begin
      `OC8051_JMP : begin
Line 2181... Line 2300...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DP;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_JNB : begin
      `OC8051_JNB : begin
Line 2200... Line 2320...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_BIT;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_JNC : begin
      `OC8051_JNC : begin
Line 2219... Line 2340...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2_PCL;
          imm_sel = `OC8051_IDS_OP2_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_CY;
          comp_sel = `OC8051_CSS_CY;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_JNZ :begin
      `OC8051_JNZ :begin
Line 2238... Line 2360...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2_PCL;
          imm_sel = `OC8051_IDS_OP2_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_AZ;
          comp_sel = `OC8051_CSS_AZ;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_JZ : begin
      `OC8051_JZ : begin
Line 2258... Line 2381...
          imm_sel = `OC8051_IDS_OP2_PCL;
          imm_sel = `OC8051_IDS_OP2_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_AZ;
          comp_sel = `OC8051_CSS_AZ;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
 
          stb_i = 1'b0;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_LCALL :begin
      `OC8051_LCALL :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
Line 2276... Line 2400...
          pc_wr = `OC8051_PCW_Y;
          pc_wr = `OC8051_PCW_Y;
          pc_sel = `OC8051_PIS_I16;
          pc_sel = `OC8051_PIS_I16;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_LJMP : begin
      `OC8051_LJMP : begin
Line 2295... Line 2420...
          pc_wr = `OC8051_PCW_Y;
          pc_wr = `OC8051_PCW_Y;
          pc_sel = `OC8051_PIS_I16;
          pc_sel = `OC8051_PIS_I16;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_D : begin
      `OC8051_MOV_D : begin
Line 2314... Line 2440...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_C : begin
      `OC8051_MOV_C : begin
Line 2333... Line 2460...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
 
 
Line 2353... Line 2481...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_DD : begin
      `OC8051_MOV_DD : begin
Line 2372... Line 2501...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_CD : begin
      `OC8051_MOV_CD : begin
Line 2391... Line 2521...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3;
          imm_sel = `OC8051_IDS_OP3;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_BC : begin
      `OC8051_MOV_BC : begin
Line 2410... Line 2541...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_CB : begin
      `OC8051_MOV_CB : begin
Line 2429... Line 2561...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3;
          imm_sel = `OC8051_IDS_OP3;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOV_DP : begin  ///***
      `OC8051_MOV_DP : begin  ///***
Line 2448... Line 2581...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_OP2;
          imm_sel = `OC8051_IDS_OP3_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOVC_DP :begin
      `OC8051_MOVC_DP :begin
Line 2467... Line 2601...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DP;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOVC_PC : begin
      `OC8051_MOVC_PC : begin
Line 2486... Line 2621...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_PCL;
          imm_sel = `OC8051_IDS_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_MOVX_PA : begin
      `OC8051_MOVX_PA : begin
Line 2505... Line 2641...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
        end
        end
      `OC8051_MOVX_AP : begin
      `OC8051_MOVX_AP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
Line 2523... Line 2660...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
        end
        end
      `OC8051_MUL : begin
      `OC8051_MUL : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
Line 2541... Line 2679...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ORL_D : begin
      `OC8051_ORL_D : begin
Line 2560... Line 2699...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ORL_C : begin
      `OC8051_ORL_C : begin
Line 2579... Line 2719...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ORL_AD : begin
      `OC8051_ORL_AD : begin
Line 2598... Line 2739...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ORL_CD : begin
      `OC8051_ORL_CD : begin
Line 2617... Line 2759...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3;
          imm_sel = `OC8051_IDS_OP3;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ORL_B : begin
      `OC8051_ORL_B : begin
Line 2636... Line 2779...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_ORL_NB : begin
      `OC8051_ORL_NB : begin
Line 2655... Line 2799...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_POP : begin
      `OC8051_POP : begin
Line 2674... Line 2819...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_PUSH : begin
      `OC8051_PUSH : begin
Line 2693... Line 2839...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_RET : begin
      `OC8051_RET : begin
Line 2712... Line 2859...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_RETI : begin
      `OC8051_RETI : begin
Line 2731... Line 2879...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_RL : begin
      `OC8051_RL : begin
Line 2750... Line 2899...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_RLC : begin
      `OC8051_RLC : begin
Line 2769... Line 2919...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_RR : begin
      `OC8051_RR : begin
Line 2788... Line 2939...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_RRC : begin
      `OC8051_RRC : begin
Line 2807... Line 2959...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_SETB_C : begin
      `OC8051_SETB_C : begin
Line 2826... Line 2979...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_SETB_B : begin
      `OC8051_SETB_B : begin
Line 2845... Line 2999...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_SJMP : begin
      `OC8051_SJMP : begin
Line 2864... Line 3019...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2_PCL;
          imm_sel = `OC8051_IDS_OP2_PCL;
          src_sel3 = `OC8051_AS3_PC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_SUBB_D : begin
      `OC8051_SUBB_D : begin
Line 2883... Line 3039...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_SUBB_C : begin
      `OC8051_SUBB_C : begin
Line 2902... Line 3059...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_SWAP : begin
      `OC8051_SWAP : begin
Line 2921... Line 3079...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_XCH_D : begin
      `OC8051_XCH_D : begin
Line 2940... Line 3099...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_Y;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_XRL_D : begin
      `OC8051_XRL_D : begin
Line 2959... Line 3119...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_XRL_C : begin
      `OC8051_XRL_C : begin
Line 2978... Line 3139...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_XRL_AD : begin
      `OC8051_XRL_AD : begin
Line 2997... Line 3159...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      `OC8051_XRL_CD : begin
      `OC8051_XRL_CD : begin
Line 3016... Line 3179...
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3;
          imm_sel = `OC8051_IDS_OP3;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
        end
        end
      default: begin
      default: begin
Line 3035... Line 3199...
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
 
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
 
 
       end
       end
 
 
Line 3059... Line 3224...
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    state <= #1 2'b01;
    state <= #1 2'b01;
  else if (istb_t && !iack) begin
  else if (istb_t && !iack) begin
    state <= #1 2'b01;
    state <= #1 2'b10;
  end else begin
  end else begin
    case (state)
    case (state)
      2'b10: state <= #1 2'b01;
      2'b10: state <= #1 2'b01;
      2'b11: state <= #1 2'b10;
      2'b11: state <= #1 2'b10;
      2'b00:
      2'b00:
Line 3076... Line 3241...
          `OC8051_CJNE_C : state <= #1 2'b11;
          `OC8051_CJNE_C : state <= #1 2'b11;
          `OC8051_LJMP : state <= #1 2'b01;
          `OC8051_LJMP : state <= #1 2'b01;
          `OC8051_DJNZ_R :state <= #1 2'b11;
          `OC8051_DJNZ_R :state <= #1 2'b11;
          `OC8051_DJNZ_D :state <= #1 2'b11;
          `OC8051_DJNZ_D :state <= #1 2'b11;
          `OC8051_LCALL :state <= #1 2'b01;
          `OC8051_LCALL :state <= #1 2'b01;
          `OC8051_MOVC_DP :state <= #1 2'b10;
          `OC8051_MOVC_DP :state <= #1 2'b11;
          `OC8051_MOVC_PC :state <= #1 2'b10;
          `OC8051_MOVC_PC :state <= #1 2'b11;
          `OC8051_RET : state <= #1 2'b11;
          `OC8051_RET : state <= #1 2'b11;
          `OC8051_RETI : state <= #1 2'b11;
          `OC8051_RETI : state <= #1 2'b11;
          `OC8051_SJMP : state <= #1 2'b10;
          `OC8051_SJMP : state <= #1 2'b10;
          `OC8051_JB : state <= #1 2'b10;
          `OC8051_JB : state <= #1 2'b10;
          `OC8051_JBC : state <= #1 2'b10;
          `OC8051_JBC : state <= #1 2'b10;
Line 3196... Line 3361...
 
 
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    istb_t <= #1 1'b0;
    istb_t <= #1 1'b0;
  else if (((op_in == `OC8051_MOVC_DP) || (op_in == `OC8051_MOVC_PC)) && !ea)
 
    istb_t <= #1 1'b1;
 
  else if (iack)
  else if (iack)
    istb_t <= #1 1'b0;
    istb_t <= #1 1'b0;
 
  else if (((op_cur== `OC8051_MOVC_DP) || (op_cur == `OC8051_MOVC_PC)) && !ea)
 
    istb_t <= #1 1'b1;
end
end
 
 
endmodule
endmodule
 
 
 
 

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