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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_defines.v] - Diff between revs 118 and 120

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Rev 118 Rev 120
Line 44... Line 44...
//
//
// ver: 1
// ver: 1
//
//
 
 
//
//
 
// oc8051 pherypherals
 
//
 
`define OC8051_UART
 
`define OC8051_TC01
 
`define OC8051_TC2
 
`define OC8051_PORTS  //ports global enable
 
`define OC8051_PORT0
 
`define OC8051_PORT1
 
`define OC8051_PORT2
 
`define OC8051_PORT3
 
 
 
 
 
 
 
//
// oc8051 memory
// oc8051 memory
//
//
//`define OC8051_CACHE
//`define OC8051_CACHE
`define OC8051_XILINX_ROM
`define OC8051_XILINX_ROM
 
 

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