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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_defines.v] - Diff between revs 118 and 120
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Rev 120 |
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//
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//
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// ver: 1
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// ver: 1
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//
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//
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//
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//
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// oc8051 pherypherals
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//
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`define OC8051_UART
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`define OC8051_TC01
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`define OC8051_TC2
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`define OC8051_PORTS //ports global enable
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`define OC8051_PORT0
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`define OC8051_PORT1
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`define OC8051_PORT2
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`define OC8051_PORT3
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//
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// oc8051 memory
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// oc8051 memory
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//
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//
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//`define OC8051_CACHE
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//`define OC8051_CACHE
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`define OC8051_XILINX_ROM
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`define OC8051_XILINX_ROM
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