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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_defines.v] - Diff between revs 126 and 132

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Rev 126	Rev 132
Line 374...	Line 374...
`define OC8051_RRS_D 3'b010 // direct addressing	`define OC8051_RRS_D 3'b010 // direct addressing
`define OC8051_RRS_SP 3'b011 // stack pointer	`define OC8051_RRS_SP 3'b011 // stack pointer

`define OC8051_RRS_B 3'b100 // b register	`define OC8051_RRS_B 3'b100 // b register
`define OC8051_RRS_DPTR 3'b101 // data pointer	`define OC8051_RRS_DPTR 3'b101 // data pointer
	`define OC8051_RRS_PSW 3'b110 // program status word
	`define OC8051_RRS_ACC 3'b111 // acc

`define OC8051_RRS_DC 3'b000 // don't c	`define OC8051_RRS_DC 3'b000 // don't c

`//`	`//`
`// ram write select`	`// ram write select`
Line 396...	Line 398...
`// pc in select`	`// pc in select`
`//`	`//`
`define OC8051_PIS_DC 3'b000 // dont c	`define OC8051_PIS_DC 3'b000 // dont c
`define OC8051_PIS_AL 3'b000 // alu low	`define OC8051_PIS_AL 3'b000 // alu low
`define OC8051_PIS_AH 3'b001 // alu high	`define OC8051_PIS_AH 3'b001 // alu high
`define OC8051_PIS_ALU 3'b010 // alu {des1, des2}	`define OC8051_PIS_SO1 3'b010 // relative address, op1
`define OC8051_PIS_I11 3'b011 // 11 bit immediate	`define OC8051_PIS_SO2 3'b011 // relative address, op2
`define OC8051_PIS_I16 3'b100 // 16 bit immediate	`define OC8051_PIS_I11 3'b100 // 11 bit immediate
	`define OC8051_PIS_I16 3'b101 // 16 bit immediate
	`define OC8051_PIS_ALU 3'b110 // alu destination {des2, des1}

`//`	`//`
`// compare source select`	`// compare source select`
`//`	`//`
`define OC8051_CSS_AZ 2'b00 // eq = accumulator == zero	`define OC8051_CSS_AZ 2'b00 // eq = accumulator == zero
`define OC8051_CSS_DES 2'b01 // eq = destination == zero	`define OC8051_CSS_DES 2'b01 // eq = destination == zero
`define OC8051_CSS_CY 2'b10 // eq = cy	`define OC8051_CSS_CY 2'b10 // eq = cy
`define OC8051_CSS_BIT 2'b11 // eq = b_in	`define OC8051_CSS_BIT 2'b11 // eq = b_in
`define OC8051_CSS_DC 2'b00 // don't care	`define OC8051_CSS_DC 2'b01 // don't care


`//`	`//`
`// pc Write`	`// pc Write`
`//`	`//`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_defines.v] - Diff between revs 126 and 132