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Line 69... |
output desOv;
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output desOv;
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output [7:0] des1, des2;
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output [7:0] des1, des2;
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// wires
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// wires
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reg desOv;
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reg desOv;
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wire div0, div1, div2, div3;
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wire div0, div1;
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wire [7:0] rem1, rem2, rem3, rem4;
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wire [7:0] rem1, rem2;
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wire [15:0] cmp0, cmp1, cmp2, cmp3;
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wire [15:0] cmp0, cmp1;
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reg [7:0] div_out, rem_out;
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reg [7:0] div_out, rem_out;
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wire [7:0] div;
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wire [7:0] div;
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// real registers
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// real registers
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reg cycle;
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reg cycle;
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reg [3:0] tmp_div;
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reg [5:0] tmp_div;
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reg [7:0] tmp_rem;
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reg [7:0] tmp_rem;
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/* This logic is very much redundant, but it should be optimized by
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/* This logic is very redundant, but it should be optimized by
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synthesizer */
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synthesizer */
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assign cmp3 = src2 << (cycle ? 3'h7 : 3'h3);
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assign cmp1 = src2 << ({1'b0, cycle} * 3'h2 + 3'h1);
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assign cmp2 = src2 << (cycle ? 3'h6 : 3'h2);
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assign cmp0 = src2 << ({1'b0, cycle} * 3'h2 + 3'h0);
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assign cmp1 = src2 << (cycle ? 3'h5 : 3'h1);
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assign cmp0 = src2 << (cycle ? 3'h4 : 3'h0);
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assign rem2 = cycle != 0 ? tmp_rem : src1;
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assign rem4 = cycle ? tmp_rem : src1;
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assign div3 = cmp3 <= rem4;
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assign rem3 = rem4 - (div3 ? cmp3[7:0] : 8'h0);
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assign div2 = cmp2 <= rem3;
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assign rem2 = rem3 - (div2 ? cmp2[7:0] : 8'h0);
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assign div1 = cmp1 <= rem2;
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assign div1 = cmp1 <= rem2;
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assign rem1 = rem2 - (div1 ? cmp1[7:0] : 8'h0);
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assign rem1 = rem1 - (div1 ? cmp1[7:0] : 8'h0);
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assign div0 = cmp0 <= rem1;
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assign div0 = cmp0 <= rem1;
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//
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//
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// in clock cycle 0 we first calculate four MSB bits,
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// in clock cycle 0 we first calculate two MSB bits, ...
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// and four LSB in cycle 1
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// till finally in clock cycle 3 we calculate two LSB bits
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always @(rem1 or div0 or div1 or div2 or div3 or cmp0 or tmp_div)
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always @(rem1 or div0 or cmp0 or tmp_div or src2)
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begin
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begin
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if (src2 == 8'h0) begin
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if (src2 == 8'h0) begin
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desOv = 1'b1;
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desOv = 1'b1;
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div_out = 8'hx;
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div_out = 8'hx;
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rem_out = 8'hx;
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rem_out = 8'hx;
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end else begin
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end else begin
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desOv = 1'b0;
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desOv = 1'b0;
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rem_out = rem1 - (div0 ? cmp0[7:0] : 8'h0);
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rem_out = rem1 - (div0 ? cmp0[7:0] : 8'h0);
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div_out = {tmp_div, div3, div2, div1, div0};
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div_out = {div1, div0, tmp_div};
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end
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end
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end
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end
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//
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//
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// divider works in two clock cycles -- 0 and 1
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// divider works in four clock cycles -- 0, 1, 2 and 3
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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cycle <= #1 1'b0;
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cycle <= #1 1'b0;
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tmp_div <= #1 4'h0;
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tmp_div <= #1 6'h0;
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tmp_rem <= #1 8'h0;
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tmp_rem <= #1 8'h0;
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end else begin
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end else begin
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if (enable && !cycle) cycle <= #1 1'b1;
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if (enable && !cycle) cycle <= #1 1'b1;
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else cycle <= #1 1'b0;
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else cycle <= #1 1'b0;
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tmp_div <= #1 div_out[3:0];
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tmp_div <= #1 div_out[7:2];
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tmp_rem <= #1 rem_out;
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tmp_rem <= #1 rem_out;
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end
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end
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end
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end
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//
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//
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