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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Two cycle implementation of division used in alu.v ////
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//// Four cycle implementation of division used in alu.v ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// check if compiler does proper optimizations of the code ////
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//// check if compiler does proper optimizations of the code ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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input [7:0] src1, src2;
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input [7:0] src1, src2;
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output desOv;
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output desOv;
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output [7:0] des1, des2;
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output [7:0] des1, des2;
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// wires
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// wires
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reg desOv;
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wire desOv;
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wire div0, div1;
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wire div0, div1;
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wire [7:0] rem1, rem2;
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wire [7:0] rem0, rem1, rem2;
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wire [8:0] sub0, sub1;
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wire [15:0] cmp0, cmp1;
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wire [15:0] cmp0, cmp1;
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reg [7:0] div_out, rem_out;
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wire [7:0] div_out, rem_out;
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wire [7:0] div;
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wire [7:0] div;
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// real registers
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// real registers
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reg [1:0] cycle;
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reg [1:0] cycle;
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reg [5:0] tmp_div;
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reg [5:0] tmp_div;
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reg [7:0] tmp_rem;
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reg [7:0] tmp_rem;
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/* This logic is very redundant, but it should be optimized by
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// The main logic
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synthesizer */
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assign cmp1 = src2 << ({2'h3 - cycle, 1'b0} + 3'h1);
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assign cmp1 = src2 << ({2'h3 - cycle, 1'b0} + 3'h1);
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assign cmp0 = src2 << ({2'h3 - cycle, 1'b0} + 3'h0);
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assign cmp0 = src2 << ({2'h3 - cycle, 1'b0} + 3'h0);
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assign rem2 = cycle != 0 ? tmp_rem : src1;
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assign rem2 = cycle != 0 ? tmp_rem : src1;
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assign div1 = cmp1 <= rem2;
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assign rem1 = rem2 - (div1 ? cmp1[7:0] : 8'h0);
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assign sub1 = {1'b0, rem2} - {1'b0, cmp1[7:0]};
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assign div0 = cmp0 <= rem1;
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assign div1 = |cmp1[15:8] ? 1'b0 : !sub1[8];
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assign rem1 = div1 ? sub1[7:0] : cmp1[7:0];
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assign sub0 = {1'b0, rem1} - {1'b0, cmp0[7:0]};
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assign div0 = |cmp0[15:8] ? 1'b0 : !sub0[8];
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assign rem0 = div0 ? sub0[7:0] : cmp0[7:0];
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//
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//
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// in clock cycle 0 we first calculate two MSB bits, ...
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// in clock cycle 0 we first calculate two MSB bits, ...
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// till finally in clock cycle 3 we calculate two LSB bits
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// till finally in clock cycle 3 we calculate two LSB bits
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always @(rem1 or div0 or cmp0 or tmp_div or src2)
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assign div_out = {tmp_div, div1, div0};
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begin
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assign rem_out = rem0;
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if (src2 == 8'h0) begin
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assign desOv = src2 == 8'h0;
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desOv = 1'b1;
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div_out = 8'hx;
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rem_out = 8'hx;
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end else begin
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desOv = 1'b0;
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rem_out = rem1 - (div0 ? cmp0[7:0] : 8'h0);
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div_out = {tmp_div, div1, div0};
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end
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end
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//
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//
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// divider works in four clock cycles -- 0, 1, 2 and 3
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// divider works in four clock cycles -- 0, 1, 2 and 3
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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