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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Implementation of division used in alu.v ////
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//// Two cycle implementation of division used in alu.v ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Nothing ////
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//// check if compiler does proper optimizations of the code ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Marko Mlinar, markom@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// ver: 1
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// ver: 1
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//
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//
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// ver: 2 markom
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// changed nonsynthesizable version to two cycle divison
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_divide (src1, src2, des1, des2, desOv);
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module oc8051_divide (clk, rst, enable, src1, src2, des1, des2, desOv);
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//
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//
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// this module is part of alu
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// this module is part of alu
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// clk (in)
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// rst (in)
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// enable (in) starts divison
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// src1 (in) first operand
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// src1 (in) first operand
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// src2 (in) second operand
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// src2 (in) second operand
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// des1 (out) first result
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// des1 (out) first result
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// des2 (out) second result
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// des2 (out) second result
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// desOv (out) Overflow output
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// desOv (out) Overflow output
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//
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//
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input clk, rst, enable;
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input [7:0] src1, src2;
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input [7:0] src1, src2;
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output desOv;
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output desOv;
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output [7:0] des1, des2;
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output [7:0] des1, des2;
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reg desOv; reg [7:0] des1, des2;
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reg [8:0] div1,div2;
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always @(src1 or src2)
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// wires
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reg desOv;
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reg div0, div1, div2, div3;
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reg [7:0] rem1, rem2, rem3;
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reg [15:0] cmp0, cmp1, cmp2, cmp3;
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reg [7:0] div_out, rem_out;
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wire [7:0] div, rem;
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// real registers
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reg cycle;
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reg [3:0] tmp_div;
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reg [7:0] tmp_rem;
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assign rem = cycle ? tmp_rem : src1;
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//
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// in clock cycle 0 we first calculate four MSB bits,
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// and four LSB in cycle 1
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always @(src2 or tmp_div or rem or cycle)
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begin
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begin
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if (src2==8'b0000_0000) begin
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if (src2==8'b0000_0000) begin
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des1=8'bxxxx_xxxx;
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desOv <= 1'b1;
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des2=8'bxxxx_xxxx;
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div_out <= 8'hxxxx_xxxx;
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desOv=1'b1;
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rem_out <= 8'hxxxx_xxxx;
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end
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end else begin
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else if (src1==src2) begin
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desOv <= 1'b0;
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des1=8'b0000_0001;
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des2=8'b0000_0000;
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/* This logic is very much redundant, but it should be optimized by
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desOv=1'b0;
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synthesizer */
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end
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cmp3 <= src2 << (cycle ? 3'h7 : 3'h3);
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else if (src1<src2) begin
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cmp2 <= src2 << (cycle ? 3'h6 : 3'h2);
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des1=8'b0000_0000;
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cmp1 <= src2 << (cycle ? 3'h5 : 3'h1);
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des2=src1;
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cmp0 <= src2 << (cycle ? 3'h4 : 3'h0);
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desOv=1'b0;
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div3 <= cmp3 <= rem;
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div2 <= cmp2 <= rem3;
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div1 <= cmp1 <= rem2;
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div0 <= cmp0 <= rem1;
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rem3 <= rem - (div3 ? cmp3 : 8'h0);
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rem2 <= rem3 - (div2 ? cmp2 : 8'h0);
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rem1 <= rem2 - (div1 ? cmp1 : 8'h0);
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rem_out <= rem1 - (div0 ? cmp0 : 8'h0);
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div_out <= {tmp_div, div3, div2, div1, div0};
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end
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end
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else begin
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des1=src1;
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des2=8'b0000_0000;
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div2={1'b0,src2};
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// begin loop
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//loop 0
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des2={des2[6:0],des1[7]};
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des1={des1[6:0], 1'b0};
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div1={1'b1, des2};
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div1= div1 - div2;
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if (div1[8]==1'b1) begin
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des1[0]= 1'b1;
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des2=div1[7:0];
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end
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end
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//loop 1
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//
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des2={des2[6:0],des1[7]};
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// divider works in two clock cycles -- 0 and 1
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des1={des1[6:0], 1'b0};
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always @(posedge clk or posedge rst)
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div1={1'b1, des2};
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begin
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div1= div1 - div2;
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if (rst) begin
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cycle <= #1 1'b0;
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if (div1[8]==1'b1) begin
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tmp_div <= #1 4'h0;
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des1[0]= 1'b1;
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tmp_rem <= #1 8'h0;
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des2=div1[7:0];
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end else begin
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end
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if (enable && !cycle) cycle <= #1 1'b1;
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//loop 2
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else cycle <= #1 1'b0;
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des2={des2[6:0],des1[7]};
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tmp_div <= #1 div_out[3:0];
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des1={des1[6:0], 1'b0};
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tmp_rem <= #1 rem_out;
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div1={1'b1, des2};
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div1= div1 - div2;
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if (div1[8]==1'b1) begin
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des1[0]= 1'b1;
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des2=div1[7:0];
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end
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//loop 3
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des2={des2[6:0],des1[7]};
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des1={des1[6:0], 1'b0};
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div1={1'b1, des2};
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div1= div1 - div2;
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if (div1[8]==1'b1) begin
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des1[0]= 1'b1;
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des2=div1[7:0];
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end
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//loop 4
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des2={des2[6:0],des1[7]};
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des1={des1[6:0], 1'b0};
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div1={1'b1, des2};
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div1= div1 - div2;
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if (div1[8]==1'b1) begin
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des1[0]= 1'b1;
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des2=div1[7:0];
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end
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//loop 5
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des2={des2[6:0],des1[7]};
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des1={des1[6:0], 1'b0};
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div1={1'b1, des2};
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div1= div1 - div2;
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if (div1[8]==1'b1) begin
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des1[0]= 1'b1;
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des2=div1[7:0];
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end
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//loop 6
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des2={des2[6:0],des1[7]};
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des1={des1[6:0], 1'b0};
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div1={1'b1, des2};
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div1= div1 - div2;
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if (div1[8]==1'b1) begin
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des1[0]= 1'b1;
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des2=div1[7:0];
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end
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end
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//loop 7
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des2={des2[6:0],des1[7]};
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des1={des1[6:0], 1'b0};
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div1={1'b1, des2};
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div1= div1 - div2;
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if (div1[8]==1'b1) begin
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des1[0]= 1'b1;
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des2=div1[7:0];
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end
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end
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//
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// end loop
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// assign outputs
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desOv=1'b0;
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assign des1 = rem_out;
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end
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assign des2 = div_out;
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end
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endmodule
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endmodule
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