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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_icache.v] - Diff between revs 67 and 82
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| Rev 67 |
Rev 82 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/10/24 13:34:02 simont
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// add parameters for instruction cache
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//
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// Revision 1.1 2002/10/23 16:55:36 simont
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// Revision 1.1 2002/10/23 16:55:36 simont
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// fix bugs in instruction interface
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// fix bugs in instruction interface
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//
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//
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//
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//
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Line 212... |
stb_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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data1_i<= #1 32'd0;
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data1_i<= #1 32'd0;
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wr1 <= #1 1'b0;
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wr1 <= #1 1'b0;
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adr_w <= #1 6'd0;
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adr_w <= #1 6'd0;
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vaild <= #1 16'd0;
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vaild <= #1 16'd0;
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end if (stb_b && !hit && !stb_o && !wr1) begin
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end else if (stb_b && !hit && !stb_o && !wr1) begin
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cyc <= #1 'd0;
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cyc <= #1 'd0;
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cyc_o <= #1 1'b1;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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data1_i<= #1 32'h0;
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data1_i<= #1 32'h0;
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wr1 <= #1 1'b0;
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wr1 <= #1 1'b0;
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end if (stb_o && ack_i) begin
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end else if (stb_o && ack_i) begin
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data1_i<= #1 dat_i;
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data1_i<= #1 dat_i;
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wr1 <= #1 1'b1;
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wr1 <= #1 1'b1;
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adr_w <= #1 adr_o[ADR_WIDTH+1:2];
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adr_w <= #1 adr_o[ADR_WIDTH+1:2];
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if (&cyc) begin
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if (&cyc) begin
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cyc <= #1 2'b00;
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cyc <= #1 2'b00;
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Line 233... |
end else begin
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end else begin
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cyc <= #1 cyc + 1'b1;
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cyc <= #1 cyc + 1'b1;
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cyc_o <= #1 1'b1;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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end
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/* case (cyc)
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2'b00: begin
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cyc <= #1 2'b01;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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2'b01: begin
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cyc <= #1 2'b10;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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2'b10: begin
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cyc <= #1 2'b11;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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default: begin
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cyc <= #1 2'b00;
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cyc_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];
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vaild[mis_adr[7:4]] <= #1 1'b1;
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end
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endcase*/
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end else begin
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end else begin
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wr1 <= #1 1'b0;
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wr1 <= #1 1'b0;
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end
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end
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end
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end
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