| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2003/01/13 14:14:41 simont
|
|
// replace some modules
|
|
//
|
// Revision 1.2 2002/10/24 13:34:02 simont
|
// Revision 1.2 2002/10/24 13:34:02 simont
|
// add parameters for instruction cache
|
// add parameters for instruction cache
|
//
|
//
|
// Revision 1.1 2002/10/23 16:55:36 simont
|
// Revision 1.1 2002/10/23 16:55:36 simont
|
// fix bugs in instruction interface
|
// fix bugs in instruction interface
|
| Line 102... |
Line 105... |
//
|
//
|
// internal buffers adn wires
|
// internal buffers adn wires
|
//
|
//
|
// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache
|
// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache
|
reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
|
reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
|
// viald[x]=1 if block x is vaild;
|
// valid[x]=1 if block x is valid;
|
reg [BL_NUM:0] vaild;
|
reg [BL_NUM:0] valid;
|
// con0, con2 contain temporal control information of current address and corrent address+2
|
// con0, con2 contain temporal control information of current address and corrent address+2
|
// part of con_buf memory
|
// part of con_buf memory
|
reg [14-ADR_WIDTH:0] con0, con2;
|
reg [14-ADR_WIDTH:0] con0, con2;
|
//current upper address,
|
//current upper address,
|
reg [13-ADR_WIDTH:0] cadr0, cadr2;
|
reg [13-ADR_WIDTH:0] cadr0, cadr2;
|
| Line 171... |
Line 174... |
end
|
end
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst)
|
|
begin
|
con0 <= #1 9'h0;
|
con0 <= #1 9'h0;
|
con2 <= #1 9'h0;
|
con2 <= #1 9'h0;
|
end else begin
|
end
|
con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]], vaild[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
|
else
|
con2 <= #1 {con_buf[adr_i2], vaild[adr_i2]};
|
begin
|
|
con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]], valid[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
|
|
con2 <= #1 {con_buf[adr_i2], valid[adr_i2]};
|
end
|
end
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
| Line 204... |
Line 210... |
end
|
end
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst)
|
|
begin
|
cyc <= #1 2'b00;
|
cyc <= #1 2'b00;
|
cyc_o <= #1 1'b0;
|
cyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
data1_i<= #1 32'd0;
|
data1_i<= #1 32'h0;
|
wr1 <= #1 1'b0;
|
wr1 <= #1 1'b0;
|
adr_w <= #1 6'd0;
|
adr_w <= #1 6'h0;
|
vaild <= #1 16'd0;
|
valid <= #1 16'h0;
|
end else if (stb_b && !hit && !stb_o && !wr1) begin
|
end
|
cyc <= #1 'd0;
|
else if (stb_b && !hit && !stb_o && !wr1)
|
|
begin
|
|
cyc <= #1 2'b00;
|
cyc_o <= #1 1'b1;
|
cyc_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
data1_i<= #1 32'h0;
|
data1_i<= #1 32'h0;
|
wr1 <= #1 1'b0;
|
wr1 <= #1 1'b0;
|
end else if (stb_o && ack_i) begin
|
end
|
|
else if (stb_o && ack_i)
|
|
begin
|
data1_i<= #1 dat_i;
|
data1_i<= #1 dat_i;
|
wr1 <= #1 1'b1;
|
wr1 <= #1 1'b1;
|
adr_w <= #1 adr_o[ADR_WIDTH+1:2];
|
adr_w <= #1 adr_o[ADR_WIDTH+1:2];
|
if (&cyc) begin
|
|
|
if (&cyc)
|
|
begin
|
cyc <= #1 2'b00;
|
cyc <= #1 2'b00;
|
cyc_o <= #1 1'b0;
|
cyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
|
// con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
|
vaild[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
|
valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
|
end else begin
|
end
|
|
else
|
|
begin
|
cyc <= #1 cyc + 1'b1;
|
cyc <= #1 cyc + 1'b1;
|
cyc_o <= #1 1'b1;
|
cyc_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
end
|
end
|
end else begin
|
|
wr1 <= #1 1'b0;
|
|
|
/* case (cyc)
|
|
2'b00: begin
|
|
cyc <= #1 2'b01;
|
|
cyc_o <= #1 1'b1;
|
|
stb_o <= #1 1'b1;
|
|
end
|
|
2'b01: begin
|
|
cyc <= #1 2'b10;
|
|
cyc_o <= #1 1'b1;
|
|
stb_o <= #1 1'b1;
|
|
end
|
|
2'b10: begin
|
|
cyc <= #1 2'b11;
|
|
cyc_o <= #1 1'b1;
|
|
stb_o <= #1 1'b1;
|
|
end
|
|
default: begin
|
|
cyc <= #1 2'b00;
|
|
cyc_o <= #1 1'b0;
|
|
stb_o <= #1 1'b0;
|
|
con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];
|
|
valid[mis_adr[7:4]] <= #1 1'b1;
|
|
end
|
|
endcase*/
|
end
|
end
|
|
else
|
|
wr1 <= #1 1'b0;
|
end
|
end
|
|
|
|
//rih
|
|
always @(posedge clk)
|
|
if ( ~(stb_b && !hit && !stb_o && !wr1) & (stb_o && ack_i & &cyc) )
|
|
con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
mis_adr <= #1 'd0;
|
mis_adr <= #1 1'b0;
|
else if (!hit_l)
|
else if (!hit_l)
|
mis_adr <= #1 adr_i;
|
mis_adr <= #1 adr_i;
|
else if (!hit_h)
|
else if (!hit_h)
|
mis_adr <= #1 adr_i+'d2;
|
mis_adr <= #1 adr_i+'d2;
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tmp_data1 <= #1 'd0;
|
tmp_data1 <= #1 1'b0;
|
else if (!hit_h && wr1 && (cyc==adr_r1))
|
else if (!hit_h && wr1 && (cyc==adr_r1))
|
tmp_data1 <= #1 dat_i[31:16];
|
tmp_data1 <= #1 dat_i[31:16];
|
else if (!hit_l && hit_h && wr1)
|
else if (!hit_l && hit_h && wr1)
|
tmp_data1 <= #1 data1_o[31:16];
|
tmp_data1 <= #1 data1_o[31:16];
|
end
|
end
|
| Line 271... |
Line 318... |
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
