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Line 67... |
input clk, rst, wr, sel, wr_bit;
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input clk, rst, wr, sel, wr_bit;
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input [1:0] bank;
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input [1:0] bank;
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input [7:0] addr, data_in;
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input [7:0] addr, data_in;
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output [7:0] data_out;
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output [7:0] data_out;
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reg [7:0] data_out;
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reg [7:0] buff [7:0];
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reg [7:0] buff [7:0];
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//
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//
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//write to buffer
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//write to buffer
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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buff[3'b000] <= #1 8'h00;
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buff[3'b000] = #1 8'h00;
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buff[3'b001] <= #1 8'h00;
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buff[3'b001] = #1 8'h00;
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buff[3'b010] <= #1 8'h00;
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buff[3'b010] = #1 8'h00;
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buff[3'b011] <= #1 8'h00;
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buff[3'b011] = #1 8'h00;
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buff[3'b100] <= #1 8'h00;
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buff[3'b100] = #1 8'h00;
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buff[3'b101] <= #1 8'h00;
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buff[3'b101] = #1 8'h00;
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buff[3'b110] <= #1 8'h00;
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buff[3'b110] = #1 8'h00;
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buff[3'b111] <= #1 8'h00;
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buff[3'b111] = #1 8'h00;
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end else begin
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end else begin
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if ((wr) & !(wr_bit)) begin
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if ((wr) & !(wr_bit)) begin
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case (addr)
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case (addr)
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8'h00: buff[3'b000] <= #1 data_in;
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8'h00: buff[3'b000] = #1 data_in;
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8'h01: buff[3'b001] <= #1 data_in;
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8'h01: buff[3'b001] = #1 data_in;
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8'h08: buff[3'b010] <= #1 data_in;
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8'h08: buff[3'b010] = #1 data_in;
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8'h09: buff[3'b011] <= #1 data_in;
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8'h09: buff[3'b011] = #1 data_in;
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8'h10: buff[3'b100] <= #1 data_in;
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8'h10: buff[3'b100] = #1 data_in;
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8'h11: buff[3'b101] <= #1 data_in;
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8'h11: buff[3'b101] = #1 data_in;
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8'h18: buff[3'b110] <= #1 data_in;
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8'h18: buff[3'b110] = #1 data_in;
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8'h19: buff[3'b111] <= #1 data_in;
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8'h19: buff[3'b111] = #1 data_in;
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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//
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//
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//read from buffer
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//read from buffer
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//always @(sel or bank or data_in or wr or addr or wr or buff)
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assign data_out = (({3'b000, bank, 2'b00, sel}==addr) & (wr)) ?
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always @(sel or bank or data_in or wr or addr or wr)
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data_in : buff[{bank, sel}];
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begin
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if (({3'b000, bank, 2'b00, sel}==addr) & (wr))
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data_out = data_in;
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else
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data_out = buff[{bank, sel}];
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end
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endmodule
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endmodule
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