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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2003/03/28 17:45:57 simont
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// change module name.
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//
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// Revision 1.6 2003/01/13 14:14:41 simont
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// Revision 1.6 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.5 2002/09/30 17:33:59 simont
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// Revision 1.5 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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//synopsys translate_on
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//synopsys translate_on
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module oc8051_int (clk, rst, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit,
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module oc8051_int (clk, rst,
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wr_addr,
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data_in, bit_in,
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wr, wr_bit,
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//timer interrupts
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//timer interrupts
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tf0, tf1, t2_int,
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tf0, tf1, t2_int,
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tr0, tr1,
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tr0, tr1,
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//external interrupts
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//external interrupts
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ie0, ie1,
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ie0, ie1,
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//uart interrupts
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//uart interrupts
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uart_int,
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uart_int,
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//to cpu
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//to cpu
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intr, reti, int_vec, ack);
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intr, reti, int_vec, ack,
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//registers
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ie, tcon, ip);
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input [7:0] wr_addr, data_in, rd_addr;
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input [7:0] wr_addr, data_in;
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input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
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input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
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output tr0, tr1, intr, bit_out;
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output tr0, tr1, intr;
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output [7:0] int_vec, data_out;
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output [7:0] int_vec,
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ie,
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tcon,
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ip;
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reg [7:0] ip, ie, int_vec, data_out;
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reg [7:0] ip, ie, int_vec;
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reg [3:0] tcon_s;
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reg [3:0] tcon_s;
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reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
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reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0;
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wire [7:0] tcon;
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//
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//
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// isrc processing interrupt sources
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// isrc processing interrupt sources
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// int_dept
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// int_dept
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wire [2:0] isrc_cur;
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wire [2:0] isrc_cur;
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Line 254... |
// ie1 (tmod.3)
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// ie1 (tmod.3)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
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tcon_ie1 <=#1 1'b0;
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tcon_ie1 <=#1 1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_ie1 <= #1 data_in[3];
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tcon_ie1 <= #1 data_in[3];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
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tcon_ie1 <= #1 bit_in;
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tcon_ie1 <= #1 bit_in;
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Line 338... |
end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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if (rst) data_out <= #1 8'h0;
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else if (wr & !wr_bit & (wr_addr==rd_addr) & (
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(wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
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data_out <= #1 data_in;
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end else begin
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case (rd_addr)
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`OC8051_SFR_IP: data_out <= #1 ip;
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`OC8051_SFR_IE: data_out <= #1 ie0;
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default: data_out <= #1 tcon;
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endcase
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end
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end
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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tf0_buff <= #1 1'b0;
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tf0_buff <= #1 1'b0;
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tf1_buff <= #1 1'b0;
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tf1_buff <= #1 1'b0;
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ie0_buff <= #1 1'b0;
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ie0_buff <= #1 1'b0;
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ie1_buff <= #1 1'b0;
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ie1_buff <= #1 1'b0;
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Line 350... |
tf1_buff <= #1 tf1;
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tf1_buff <= #1 tf1;
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ie0_buff <= #1 ie0;
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ie0_buff <= #1 ie0;
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ie1_buff <= #1 ie1;
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ie1_buff <= #1 ie1;
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end
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end
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always @(posedge clk or posedge rst)
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begin
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if (rst) bit_out <= #1 1'b0;
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else if (wr & wr_bit & (wr_addr==rd_addr)) begin
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bit_out <= #1 bit_in;
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end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin
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bit_out <= #1 data_in[rd_addr[2:0]];
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end else begin
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case (rd_addr[7:3])
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`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
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`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
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default: bit_out <= #1 tcon[rd_addr[2:0]];
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endcase
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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