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Line 44... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2003/04/07 14:58:02 simont
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// change sfr's interface.
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//
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// Revision 1.7 2003/03/28 17:45:57 simont
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// Revision 1.7 2003/03/28 17:45:57 simont
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// change module name.
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// change module name.
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//
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//
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// Revision 1.6 2003/01/13 14:14:41 simont
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// Revision 1.6 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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Line 102... |
//
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//
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// isrc processing interrupt sources
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// isrc processing interrupt sources
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// int_dept
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// int_dept
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wire [2:0] isrc_cur;
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wire [2:0] isrc_cur;
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reg [2:0] isrc [1:0];
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reg [2:0] isrc [1:0];
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reg int_dept;
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reg [1:0] int_dept;
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wire int_dept_1;
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wire [1:0] int_dept_1;
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reg int_proc;
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reg int_proc;
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reg [1:0] int_lev [1:0];
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reg [1:0] int_lev [1:0];
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wire cur_lev;
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wire cur_lev;
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assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
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assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
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assign int_dept_1 = int_dept - 1'b1;
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assign int_dept_1 = int_dept - 2'b01;
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assign cur_lev = int_lev[int_dept_1];
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assign cur_lev = int_lev[int_dept_1];
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//
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//
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// contains witch level of interrupts is running
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// contains witch level of interrupts is running
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//reg [1:0] int_levl, int_levl_w;
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//reg [1:0] int_levl, int_levl_w;
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Line 277... |
// interrupt processing
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// interrupt processing
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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int_vec <= #1 8'h00;
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int_vec <= #1 8'h00;
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int_dept <= #1 1'b0;
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int_dept <= #1 2'b0;
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isrc[0] <= #1 3'h0;
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isrc[0] <= #1 3'h0;
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isrc[1] <= #1 3'h0;
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isrc[1] <= #1 3'h0;
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int_proc <= #1 1'b0;
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int_proc <= #1 1'b0;
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int_lev[0] <= #1 1'b0;
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int_lev[0] <= #1 1'b0;
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int_lev[1] <= #1 1'b0;
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int_lev[1] <= #1 1'b0;
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end else if (reti) begin // return from interrupt
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end else if (reti & int_proc) begin // return from interrupt
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if (int_dept==2'b01)
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if (int_dept==2'b01)
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int_proc <= #1 1'b0;
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int_proc <= #1 1'b0;
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int_dept <= #1 int_dept - 2'b01;
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int_dept <= #1 int_dept - 2'b01;
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end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin // interrupt on level 1
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end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin // interrupt on level 1
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int_proc <= #1 1'b1;
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int_proc <= #1 1'b1;
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Line 314... |
end
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end
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end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0
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end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0
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int_proc <= #1 1'b1;
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int_proc <= #1 1'b1;
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int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
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int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
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int_dept <= #1 int_dept + 2'b01;
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int_dept <= #1 2'b01;
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if (int_l0[0]) begin
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if (int_l0[0]) begin
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int_vec <= #1 `OC8051_INT_X0;
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int_vec <= #1 `OC8051_INT_X0;
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isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
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isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
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end else if (int_l0[1]) begin
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end else if (int_l0[1]) begin
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int_vec <= #1 `OC8051_INT_T0;
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int_vec <= #1 `OC8051_INT_T0;
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