URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Diff between revs 4 and 17

Rev 4	Rev 17
Line 16...	Line 16...
`//reti return from interrupt signal (input)`	`//reti return from interrupt signal (input)`
`//int_src describes interrupt source (output)`	`//int_src describes interrupt source (output)`
`//ip ip register (internal)`	`//ip ip register (internal)`
`//ie ie register (internal)`	`//ie ie register (internal)`
`//tcon tcon register (internal)`	`//tcon tcon register (internal)`
`//id id register (internal)`




`include "oc8051_defines.v"	`include "oc8051_defines.v"
Line 36...	Line 35...
`input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;`	`input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;`

`output tr0, tr1, intr, bit_out;`	`output tr0, tr1, intr, bit_out;`
`output [7:0] int_vec, data_out;`	`output [7:0] int_vec, data_out;`

`reg [7:0] ip, ie, int_vec, id, data_out;`	`reg [7:0] ip, ie, int_vec, data_out;`

`reg [3:0] tcon_s;`	`reg [3:0] tcon_s;`
`reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;`	`reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;`
`wire [7:0] tcon;`	`wire [7:0] tcon;`