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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Diff between revs 150 and 179
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| Rev 150 |
Rev 179 |
| Line 44... |
Line 44... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/06/03 17:12:05 simont
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// fix some bugs.
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//
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// Revision 1.8 2003/04/07 14:58:02 simont
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// Revision 1.8 2003/04/07 14:58:02 simont
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// change sfr's interface.
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// change sfr's interface.
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//
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//
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// Revision 1.7 2003/03/28 17:45:57 simont
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// Revision 1.7 2003/03/28 17:45:57 simont
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// change module name.
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// change module name.
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Line 187... |
if (rst) begin
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if (rst) begin
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tcon_s <=#1 4'b0000;
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tcon_s <=#1 4'b0000;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
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tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
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case (wr_addr[2:0])
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case (wr_addr[2:0]) /* synopsys full_case parallel_case */
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3'b000: tcon_s[0] <= #1 bit_in;
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3'b000: tcon_s[0] <= #1 bit_in;
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3'b010: tcon_s[1] <= #1 bit_in;
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3'b010: tcon_s[1] <= #1 bit_in;
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3'b100: tcon_s[2] <= #1 bit_in;
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3'b100: tcon_s[2] <= #1 bit_in;
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3'b110: tcon_s[3] <= #1 bit_in;
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3'b110: tcon_s[3] <= #1 bit_in;
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endcase
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endcase
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