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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Diff between revs 17 and 22
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| Rev 17 |
Rev 22 |
| Line 279... |
Line 279... |
end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) bit_out <= #1 1'b0;
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if (rst) bit_out <= #1 1'b0;
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else if (wr & wr_bit & (wr_addr==rd_addr) & ((wr_addr[7:3]==`OC8051_SFR_B_IP) |
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else if (wr & wr_bit & (wr_addr==rd_addr)) begin
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(wr_addr[7:3]==`OC8051_SFR_B_IE) | (wr_addr[7:3]==`OC8051_SFR_B_TCON))) begin
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bit_out <= #1 bit_in;
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bit_out <= #1 bit_in;
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end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin
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bit_out <= #1 data_in[rd_addr[2:0]];
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end else begin
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end else begin
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case (rd_addr[7:3])
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case (rd_addr[7:3])
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`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
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`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
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`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
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`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
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default: bit_out <= #1 tcon[rd_addr[2:0]];
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default: bit_out <= #1 tcon[rd_addr[2:0]];
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