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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Diff between revs 22 and 46

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//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  8051 cores interrupt control module                         ////
 
////                                                              ////
 
////  This file is part of the 8051 cores project                 ////
 
////  http://www.opencores.org/cores/8051/                        ////
 
////                                                              ////
 
////  Description                                                 ////
 
////   contains sfr's: tcon, ip, ie;                              ////
 
////   interrupt handling                                         ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////   Nothing                                                    ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Simon Teran, simont@opencores.org                     ////
 
////      - Jaka Simsic, jakas@opencores.org                      ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
//
//
// version 1.0
// CVS Revision History
 
//
 
// $Log: not supported by cvs2svn $
//
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//clk  clock (pin)
//clk  clock (pin)

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