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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/05/05 15:46:37 simont
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// add aditional alu destination to solve critical path.
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//
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// Revision 1.5 2003/04/25 17:15:51 simont
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// Revision 1.5 2003/04/25 17:15:51 simont
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// change branch instruction execution (reduse needed clock periods).
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// change branch instruction execution (reduse needed clock periods).
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//
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//
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// Revision 1.4 2003/04/16 10:04:09 simont
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// Revision 1.4 2003/04/16 10:04:09 simont
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// chance idat_ir to 24 bit wide
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// chance idat_ir to 24 bit wide
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| Line 223... |
Line 226... |
assign ea_rom_sel = ea && ea_int;
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assign ea_rom_sel = ea && ea_int;
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assign wr_o = wr_i;
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assign wr_o = wr_i;
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assign wr_bit_o = wr_bit_i;
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assign wr_bit_o = wr_bit_i;
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assign mem_wait = dmem_wait || imem_wait;
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assign mem_wait = dmem_wait || imem_wait;
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//assign istb_o = (istb || istb_t || (!iack_i)) && !dstb_o && !ea_rom_sel;
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assign istb_o = (istb || istb_t) && !dstb_o && !ea_rom_sel;
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assign istb_o = (istb || istb_t) && !dstb_o && !ea_rom_sel;
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assign pc_wait = rd && (ea_rom_sel || (!istb_t && !(istb_o && !iack_i)));
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assign pc_wait = rd && (ea_rom_sel || (!istb_t && iack_i));
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assign wr_dat = des1;
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assign wr_dat = des1;
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/////////////////////////////
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/////////////////////////////
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//
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//
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// ram_select
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// ram_select
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//
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//
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///////////////////////////// ??????????????????????
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/////////////////////////////
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always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rd_ind)
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always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rd_ind)
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begin
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begin
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if (rd_addr_r && !rd_ind) begin
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if (rd_addr_r && !rd_ind) begin
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iram_out = sfr;
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iram_out = sfr;
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bit_out = sfr_bit;
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bit_out = sfr_bit;
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| Line 253... |
Line 255... |
//
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//
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// ram_adr_sel
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// ram_adr_sel
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//
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//
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/////////////////////////////
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/////////////////////////////
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always @(rd_sel or sp or ri or rn or imm or op1_out or dadr_o[15:0] or bank)
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always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank)
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begin
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begin
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case (rd_sel)
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case (rd_sel)
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`OC8051_RRS_RN : rd_addr = {3'h0, rn};
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`OC8051_RRS_RN : rd_addr = {3'h0, rn};
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`OC8051_RRS_I : rd_addr = ri;
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`OC8051_RRS_I : rd_addr = ri;
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`OC8051_RRS_D : rd_addr = imm;
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`OC8051_RRS_D : rd_addr = imm;
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