| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.11 2003/06/20 13:35:10 simont
|
|
// simualtion `ifdef added
|
|
//
|
// Revision 1.10 2003/06/05 11:15:02 simont
|
// Revision 1.10 2003/06/05 11:15:02 simont
|
// fix bug.
|
// fix bug.
|
//
|
//
|
// Revision 1.9 2003/06/03 17:09:57 simont
|
// Revision 1.9 2003/06/03 17:09:57 simont
|
// pipelined acces to axternal instruction interface added.
|
// pipelined acces to axternal instruction interface added.
|
| Line 395... |
Line 398... |
//
|
//
|
/////////////////////////////
|
/////////////////////////////
|
|
|
always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank)
|
always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank)
|
begin
|
begin
|
case (rd_sel)
|
case (rd_sel) /* synopsys full_case parallel_case */
|
`OC8051_RRS_RN : rd_addr = {3'h0, rn};
|
`OC8051_RRS_RN : rd_addr = {3'h0, rn};
|
`OC8051_RRS_I : rd_addr = ri;
|
`OC8051_RRS_I : rd_addr = ri;
|
`OC8051_RRS_D : rd_addr = imm;
|
`OC8051_RRS_D : rd_addr = imm;
|
`OC8051_RRS_SP : rd_addr = sp;
|
`OC8051_RRS_SP : rd_addr = sp;
|
|
|
`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
|
`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
|
`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
|
`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
|
`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW;
|
`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW;
|
`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC;
|
`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC;
|
default : rd_addr = 2'bxx;
|
// default : rd_addr = 2'bxx;
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
|
|
//
|
//
|
//
|
//
|
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
|
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
|
begin
|
begin
|
case (wr_sel)
|
case (wr_sel) /* synopsys full_case parallel_case */
|
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
|
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
|
`OC8051_RWS_I : wr_addr = ri_r;
|
`OC8051_RWS_I : wr_addr = ri_r;
|
`OC8051_RWS_D : wr_addr = imm_r;
|
`OC8051_RWS_D : wr_addr = imm_r;
|
`OC8051_RWS_SP : wr_addr = sp_w;
|
`OC8051_RWS_SP : wr_addr = sp_w;
|
`OC8051_RWS_D3 : wr_addr = imm2_r;
|
`OC8051_RWS_D3 : wr_addr = imm2_r;
|
`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
|
`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
|
default : wr_addr = 2'bxx;
|
// default : wr_addr = 2'bxx;
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
| Line 496... |
Line 499... |
end else if (dack_i) begin
|
end else if (dack_i) begin
|
dwe_o <= #1 1'b0;
|
dwe_o <= #1 1'b0;
|
dstb_o <= #1 1'b0;
|
dstb_o <= #1 1'b0;
|
dmem_wait <= #1 1'b0;
|
dmem_wait <= #1 1'b0;
|
end else begin
|
end else begin
|
case (mem_act)
|
case (mem_act) /* synopsys full_case parallel_case */
|
`OC8051_MAS_DPTR_R: begin // read from external rom: acc=(dptr)
|
`OC8051_MAS_DPTR_R: begin // read from external rom: acc=(dptr)
|
dwe_o <= #1 1'b0;
|
dwe_o <= #1 1'b0;
|
dstb_o <= #1 1'b1;
|
dstb_o <= #1 1'b1;
|
ddat_o <= #1 8'h00;
|
ddat_o <= #1 8'h00;
|
dadr_ot <= #1 {7'h0, dptr};
|
dadr_ot <= #1 {7'h0, dptr};
|
| Line 564... |
Line 567... |
end
|
end
|
end
|
end
|
|
|
always @(op_pos or idat_cur or idat_old)
|
always @(op_pos or idat_cur or idat_old)
|
begin
|
begin
|
case (op_pos)
|
case (op_pos) /* synopsys parallel_case */
|
3'b000: begin
|
3'b000: begin
|
op1 = idat_old[7:0] ;
|
op1 = idat_old[7:0] ;
|
op2 = idat_old[15:8] ;
|
op2 = idat_old[15:8] ;
|
op3 = idat_old[23:16];
|
op3 = idat_old[23:16];
|
end
|
end
|
| Line 675... |
Line 678... |
//
|
//
|
/////////////////////////////
|
/////////////////////////////
|
|
|
always @(op1_out)
|
always @(op1_out)
|
begin
|
begin
|
casex (op1_out)
|
casex (op1_out) /* synopsys parallel_case */
|
`OC8051_ACALL : op_length = 2'h2;
|
`OC8051_ACALL : op_length = 2'h2;
|
`OC8051_AJMP : op_length = 2'h2;
|
`OC8051_AJMP : op_length = 2'h2;
|
|
|
//op_code [7:3]
|
//op_code [7:3]
|
`OC8051_CJNE_R : op_length = 2'h3;
|
`OC8051_CJNE_R : op_length = 2'h3;
|
| Line 937... |
Line 940... |
if (rst) begin
|
if (rst) begin
|
pc_buf <= #1 `OC8051_RST_PC;
|
pc_buf <= #1 `OC8051_RST_PC;
|
end else if (pc_wr) begin
|
end else if (pc_wr) begin
|
//
|
//
|
//case of writing new value to pc (jupms)
|
//case of writing new value to pc (jupms)
|
case (pc_wr_sel)
|
case (pc_wr_sel) /* synopsys full_case parallel_case */
|
`OC8051_PIS_ALU: pc_buf <= #1 alu;
|
`OC8051_PIS_ALU: pc_buf <= #1 alu;
|
`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
|
`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
|
`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0];
|
`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0];
|
`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
|
`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
|
`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
|
`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
|
