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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_multiply.v] - Diff between revs 20 and 21
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| Rev 20 |
Rev 21 |
| Line 85... |
Line 85... |
assign mul_result1 = src1 * (cycle == 0 ? src2[7:6]
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assign mul_result1 = src1 * (cycle == 0 ? src2[7:6]
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: cycle == 1 ? src2[5:4]
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: cycle == 1 ? src2[5:4]
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: cycle == 2 ? src2[3:2]
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: cycle == 2 ? src2[3:2]
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: src2[1:0]);
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: src2[1:0]);
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assign mul_result = mul_result1 + {2'b0, tmp_mul};
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assign mul_result = mul_result1 + ({2'b0, tmp_mul} << {cycle, 1'b0});
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assign des1 = mul_result[7:0];
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assign des1 = mul_result[7:0];
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assign des2 = mul_result[15:8];
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assign des2 = mul_result[15:8];
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assign desOv = des2 != 8'h0;
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assign desOv = des2 != 8'h0;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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| Line 97... |
Line 97... |
if (rst) begin
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if (rst) begin
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cycle <= #1 1'b0;
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cycle <= #1 1'b0;
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tmp_mul <= #1 14'b0;
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tmp_mul <= #1 14'b0;
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end else begin
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end else begin
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if (enable || cycle != 0) cycle <= #1 cycle + 2'b1;
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if (enable || cycle != 0) cycle <= #1 cycle + 2'b1;
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tmp_mul <= #1 mul_result1[13:0];
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tmp_mul <= #1 mul_result[13:0];
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end
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end
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end
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end
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endmodule
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endmodule
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