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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_multiply.v] - Diff between revs 21 and 25
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| Rev 21 |
Rev 25 |
| Line 74... |
Line 74... |
input [7:0] src1, src2;
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input [7:0] src1, src2;
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output desOv;
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output desOv;
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output [7:0] des1, des2;
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output [7:0] des1, des2;
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// wires
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// wires
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wire [15:0] mul_result1, mul_result;
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wire [15:0] mul_result1, mul_result, shifted;
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// real registers
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// real registers
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reg [1:0] cycle;
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reg [1:0] cycle;
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reg [13:0] tmp_mul;
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reg [15:0] tmp_mul;
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assign mul_result1 = src1 * (cycle == 0 ? src2[7:6]
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assign mul_result1 = src1 * (cycle == 2'h0 ? src2[7:6]
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: cycle == 1 ? src2[5:4]
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: cycle == 2'h1 ? src2[5:4]
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: cycle == 2 ? src2[3:2]
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: cycle == 2'h2 ? src2[3:2]
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: src2[1:0]);
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: src2[1:0]);
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assign shifted = (cycle == 2'h0 ? 16'h0 : {tmp_mul[13:0], 2'b00});
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assign mul_result = mul_result1 + ({2'b0, tmp_mul} << {cycle, 1'b0});
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assign mul_result = mul_result1 + shifted;
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assign des1 = mul_result[7:0];
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assign des1 = mul_result[15:8];
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assign des2 = mul_result[15:8];
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assign des2 = mul_result[7:0];
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assign desOv = des2 != 8'h0;
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assign desOv = src2 != 8'h0;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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cycle <= #1 1'b0;
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cycle <= #1 2'b0;
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tmp_mul <= #1 14'b0;
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tmp_mul <= #1 16'b0;
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end else begin
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end else begin
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if (enable || cycle != 0) cycle <= #1 cycle + 2'b1;
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if (enable) cycle <= #1 cycle + 2'b1;
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tmp_mul <= #1 mul_result[13:0];
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tmp_mul <= #1 mul_result;
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end
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end
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end
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end
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endmodule
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endmodule
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