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//// To Do: ////
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//// To Do: ////
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//// Nothing ////
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//// Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Marko Mlinar, markom@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// ver: 1
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// ver: 1
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//
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//
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// ver: 2 markom
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// changed to two cycle multiplication, to save resources and
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// increase speed
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_multiply (src1, src2, des1, des2, desOv);
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module oc8051_multiply (clk, rst, enable, src1, src2, des1, des2, desOv);
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//
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//
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// this module is part of alu
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// this module is part of alu
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// clk (in)
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// rst (in)
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// enable (in)
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// src1 (in) first operand
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// src1 (in) first operand
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// src2 (in) second operand
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// src2 (in) second operand
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// des1 (out) first result
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// des1 (out) first result
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// des2 (out) second result
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// des2 (out) second result
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// desOv (out) Overflow output
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// desOv (out) Overflow output
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//
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//
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input clk, rst, enable;
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input [7:0] src1, src2;
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input [7:0] src1, src2;
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output desOv;
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output desOv;
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output [7:0] des1, des2;
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output [7:0] des1, des2;
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reg desOv; reg [7:0] des1, des2;
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always @(src1 or src2)
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// wires
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wire [15:0] mul_result1, mul_result;
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// real registers
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reg cycle;
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reg [11:0] tmp_mul;
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assign mul_result1 = src1 * (cycle ? src2[7:4] : src2[3:0]);
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assign mul_result = mul_result1 + tmp_mul;
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assign des1 = mul_result[7:0];
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assign des2 = mul_result[15:8];
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assign desOv = des2 != 8'h0;
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always @(posedge clk or posedge rst)
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begin
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begin
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{des2, des1} = src1* src2;
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if (rst) cycle <= #1 1'b0;
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if (des2!=8'b00000000)
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else begin
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desOv = 1'b1;
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if (enable && !cycle) cycle <= #1 1'b1;
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else
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else cycle <= #1 1'b0;
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desOv = 1'b0;
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tmp_mul <= #1 mul_result1[11:0];
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end
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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