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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Diff between revs 120 and 179

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Rev 120 Rev 179
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.9  2003/04/10 12:43:19  simont
 
// defines for pherypherals added
 
//
// Revision 1.8  2003/04/07 14:58:02  simont
// Revision 1.8  2003/04/07 14:58:02  simont
// change sfr's interface.
// change sfr's interface.
//
//
// Revision 1.7  2003/01/13 14:14:41  simont
// Revision 1.7  2003/01/13 14:14:41  simont
// replace some modules
// replace some modules
Line 166... Line 169...
`ifdef OC8051_PORT3
`ifdef OC8051_PORT3
    p3_out <= #1 `OC8051_RST_P3;
    p3_out <= #1 `OC8051_RST_P3;
`endif
`endif
  end else if (wr) begin
  end else if (wr) begin
    if (!wr_bit) begin
    if (!wr_bit) begin
      case (wr_addr)
      case (wr_addr) /* synopsys full_case parallel_case */
//
//
// bytaddresable
// bytaddresable
`ifdef OC8051_PORT0
`ifdef OC8051_PORT0
        `OC8051_SFR_P0: p0_out <= #1 data_in;
        `OC8051_SFR_P0: p0_out <= #1 data_in;
`endif
`endif
Line 186... Line 189...
`ifdef OC8051_PORT3
`ifdef OC8051_PORT3
        `OC8051_SFR_P3: p3_out <= #1 data_in;
        `OC8051_SFR_P3: p3_out <= #1 data_in;
`endif
`endif
      endcase
      endcase
    end else begin
    end else begin
      case (wr_addr[7:3])
      case (wr_addr[7:3]) /* synopsys full_case parallel_case */
 
 
//
//
// bit addressable
// bit addressable
`ifdef OC8051_PORT0
`ifdef OC8051_PORT0
        `OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
        `OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;

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