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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Diff between revs 2 and 4
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| Rev 2 |
Rev 4 |
| Line 111... |
Line 111... |
endcase
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endcase
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end
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end
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endcase
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endcase
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end
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end
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always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in)
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always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw or rd_addr)
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begin
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begin
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if (rmw) begin
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if (rmw) begin
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case (rd_addr[5:4])
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case (rd_addr[5:4])
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2'b00: data_out = p0_out;
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2'b00: data_out = p0_out;
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2'b01: data_out = p1_out;
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2'b01: data_out = p1_out;
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