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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Diff between revs 4 and 5

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Rev 4 Rev 5
Line 86... Line 86...
  if (rst) begin
  if (rst) begin
    p0_out <= #1 `OC8051_RST_P0;
    p0_out <= #1 `OC8051_RST_P0;
    p1_out <= #1 `OC8051_RST_P1;
    p1_out <= #1 `OC8051_RST_P1;
    p2_out <= #1 `OC8051_RST_P2;
    p2_out <= #1 `OC8051_RST_P2;
    p3_out <= #1 `OC8051_RST_P3;
    p3_out <= #1 `OC8051_RST_P3;
  end else
  end else if (wr) begin
    case ({wr, wr_bit})
    if (!wr_bit) begin
      2'b10: begin
 
        case (wr_addr)
        case (wr_addr)
//
//
// byte addresable
// bytaddresable
          `OC8051_SFR_P0: p0_out <= #1 data_in;
          `OC8051_SFR_P0: p0_out <= #1 data_in;
          `OC8051_SFR_P1: p1_out <= #1 data_in;
          `OC8051_SFR_P1: p1_out <= #1 data_in;
          `OC8051_SFR_P2: p2_out <= #1 data_in;
          `OC8051_SFR_P2: p2_out <= #1 data_in;
          `OC8051_SFR_P3: p3_out <= #1 data_in;
          `OC8051_SFR_P3: p3_out <= #1 data_in;
        endcase
        endcase
      end
    end else begin
      2'b11: begin
 
        case (wr_addr[7:3])
        case (wr_addr[7:3])
 
 
//
//
// bit addressable
// bit addressable
          `OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
          `OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
          `OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
          `OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
          `OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
          `OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
          `OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
          `OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
        endcase
        endcase
      end
      end
    endcase
  end
end
end
 
 
always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw or rd_addr)
always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw)
begin
begin
  if (rmw) begin
  if (rmw) begin
    case (rd_addr[5:4])
    case (rd_addr[5:4])
      2'b00: data_out = p0_out;
      2'b00: data_out = p0_out;
      2'b01: data_out = p1_out;
      2'b01: data_out = p1_out;

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