URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Diff between revs 46 and 82

Rev 46	Rev 82
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2002/09/30 17:33:59 simont`
	`// prepared header`
	`//`
`//`	`//`


`// synopsys translate_off`	`// synopsys translate_off`
`include "oc8051_timescale.v"	`include "oc8051_timescale.v"
Line 145...	Line 148...
`if (rst)`	`if (rst)`
`bit_out <= #1 1'b0;`	`bit_out <= #1 1'b0;`
`else if (rmw) begin`	`else if (rmw) begin`
`if ((wr_addr==rd_addr) & wr & wr_bit)`	`if ((wr_addr==rd_addr) & wr & wr_bit)`
`bit_out <= #1 bit_in;`	`bit_out <= #1 bit_in;`
`else if ((wr_addr[7:3]==rd_addr[7:3]) & wr & !wr_bit)`	`else if ((wr_addr[7:3]==rd_addr[7:3]) & wr)`
`bit_out <= #1 data_in[rd_addr[2:0]];`	`bit_out <= #1 data_in[rd_addr[2:0]];`
`else begin`	`else begin`
`case (rd_addr[7:3])`	`case (rd_addr[7:3])`
`OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];	`OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];
`OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];	`OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];