URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_psw.v] - Diff between revs 117 and 179

Rev 117	Rev 179
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.11 2003/04/09 15:49:42 simont`
	`// Register oc8051_sfr dato output, add signal wait_data.`
	`//`
`// Revision 1.10 2003/04/07 14:58:02 simont`	`// Revision 1.10 2003/04/07 14:58:02 simont`
`// change sfr's interface.`	`// change sfr's interface.`
`//`	`//`
`// Revision 1.9 2003/01/13 14:14:41 simont`	`// Revision 1.9 2003/01/13 14:14:41 simont`
`// replace some modules`	`// replace some modules`
Line 113...	Line 116...
`//`	`//`
`// write to psw (bit addressable)`	`// write to psw (bit addressable)`
else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))	else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))
`data[wr_addr[2:0]] <= #1 cy_in;`	`data[wr_addr[2:0]] <= #1 cy_in;`
`else begin`	`else begin`
`case (set)`	`case (set) /* synopsys full_case parallel_case */`
`OC8051_PS_CY: begin	`OC8051_PS_CY: begin
`//`	`//`
`//write carry`	`//write carry`
`data[7] <= #1 cy_in;`	`data[7] <= #1 cy_in;`
`end`	`end`