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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/09/30 17:33:59 simont
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// prepared header
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_psw (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, data_out, data_out_r, bit_out, p, cy_in, ac_in, ov_in, set);
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module oc8051_psw (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, data_out, bit_out, p, cy_in, ac_in, ov_in, set, bank_sel);
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//
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//
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// clk (in) clock
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// clk (in) clock
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// rst (in) reset
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// rst (in) reset
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// addr (in) write address [oc8051_ram_wr_sel.out]
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// addr (in) write address [oc8051_ram_wr_sel.out]
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// data_in (in) data input [oc8051_alu.des1]
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// data_in (in) data input [oc8051_alu.des1]
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// wr (in) write [oc8051_decoder.wr -r]
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// wr (in) write [oc8051_decoder.wr -r]
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// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
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// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
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// data_out (out) data output [oc8051_ram_sel.psw]
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// data_out (out) data output [oc8051_ram_sel.psw]
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// data_out_r (out) data output [oc8051_ram_sel.psw]
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// p (in) parity [oc8051_acc.p]
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// p (in) parity [oc8051_acc.p]
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// cy_in (in) input bit data [oc8051_alu.desCy]
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// cy_in (in) input bit data [oc8051_alu.desCy]
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// ac_in (in) auxiliary carry input [oc8051_alu.desAc]
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// ac_in (in) auxiliary carry input [oc8051_alu.desAc]
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// ov_in (in) overflov input [oc8051_alu.desOv]
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// ov_in (in) overflov input [oc8051_alu.desOv]
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// set (in) set psw (write to caryy, carry and overflov or carry, owerflov and ac) [oc8051_decoder.psw_set -r]
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// set (in) set psw (write to caryy, carry and overflov or carry, owerflov and ac) [oc8051_decoder.psw_set -r]
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input [1:0] set;
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input [1:0] set;
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input [2:0] rd_addr;
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input [2:0] rd_addr;
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input [7:0] wr_addr, data_in;
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input [7:0] wr_addr, data_in;
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output bit_out;
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output bit_out;
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output [1:0] bank_sel;
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output [7:0] data_out;
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output [7:0] data_out;
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output [7:0] data_out_r;
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reg bit_out;
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reg bit_out;
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reg [7:0] data;
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reg [7:0] data;
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wire wr_psw;
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wire wr_psw;
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assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
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assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
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assign data_out = wr_psw ? {data_in[7:1],p}:{data[7:1], p};
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assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
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assign data_out_r = data;
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assign data_out = data;
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//
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//
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//case writing to psw
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//case writing to psw
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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