URL https://opencores.org/ocsvn/8051/8051/trunk

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_psw.v] - Diff between revs 76 and 82

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Rev 76	Rev 82
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.8 2002/11/05 17:23:54 simont`
	`// add module oc8051_sfr, 256 bytes internal ram`
	`//`
`// Revision 1.7 2002/09/30 17:33:59 simont`	`// Revision 1.7 2002/09/30 17:33:59 simont`
`// prepared header`	`// prepared header`
`//`	`//`
`//`	`//`

Line 55...	Line 58...
`// synopsys translate_on`	`// synopsys translate_on`

`include "oc8051_defines.v"	`include "oc8051_defines.v"


`module oc8051_psw (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, data_out, bit_out, p, cy_in, ac_in, ov_in, set, bank_sel);`	`module oc8051_psw (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, data_out, bit_out, p,`
	`cy_in, ac_in, ov_in, set, bank_sel);`
`//`	`//`
`// clk (in) clock`	`// clk (in) clock`
`// rst (in) reset`	`// rst (in) reset`
`// addr (in) write address [oc8051_ram_wr_sel.out]`	`// addr (in) write address [oc8051_ram_wr_sel.out]`
`// data_in (in) data input [oc8051_alu.des1]`	`// data_in (in) data input [oc8051_alu.des1]`
Line 88...	Line 92...
`wire wr_psw;`	`wire wr_psw;`

assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);	assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);

`assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];`	`assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];`
	`//assign bank_sel = data[4:3];`
`assign data_out = data;`	`assign data_out = data;`

`//`	`//`
`//case writing to psw`	`//case writing to psw`
`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_psw.v] - Diff between revs 76 and 82