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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/06/20 13:36:37 simont
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// ram modules added.
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//
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// Revision 1.9 2003/06/17 14:17:22 simont
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// Revision 1.9 2003/06/17 14:17:22 simont
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// BIST signals added.
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// BIST signals added.
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//
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//
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// Revision 1.8 2003/04/02 16:12:04 simont
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// Revision 1.8 2003/04/02 16:12:04 simont
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// generic_dpram used
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// generic_dpram used
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Line 128... |
// wr_addr_m write address modified
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// wr_addr_m write address modified
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// wr_data_m write data modified
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// wr_data_m write data modified
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reg [7:0] wr_data_m;
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reg [7:0] wr_data_m;
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reg [7:0] rd_addr_m, wr_addr_m;
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reg [7:0] rd_addr_m, wr_addr_m;
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// bit_addr_r bit addresable instruction (registerd)
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reg bit_addr_r;
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wire rd_en;
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reg bit_addr_r,
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rd_en_r;
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reg [7:0] wr_data_r;
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wire [7:0] rd_data_m;
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reg [2:0] bit_select;
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reg [2:0] bit_select;
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assign bit_data_out = rd_data[bit_select];
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assign bit_data_out = rd_data[bit_select];
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assign rd_data = rd_en_r ? wr_data_r: rd_data_m;
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assign rd_en = (rd_addr_m == wr_addr_m) & wr;
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oc8051_ram_256x8_two_bist oc8051_idata(
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oc8051_ram_256x8_two_bist oc8051_idata(
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.clk ( clk ),
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.clk ( clk ),
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.rst ( rst ),
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.rst ( rst ),
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.rd_addr ( rd_addr_m ),
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.rd_addr ( rd_addr_m ),
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.rd_data ( rd_data ),
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.rd_data ( rd_data_m ),
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.rd_en ( 1'b1 ),
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.rd_en ( !rd_en ),
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.wr_addr ( wr_addr_m ),
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.wr_addr ( wr_addr_m ),
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.wr_data ( wr_data_m ),
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.wr_data ( wr_data_m ),
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.wr_en ( 1'b1 ),
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.wr_en ( 1'b1 ),
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.wr ( wr )
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.wr ( wr )
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`ifdef OC8051_BIST
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`ifdef OC8051_BIST
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Line 172... |
bit_addr_r <= #1 bit_addr;
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bit_addr_r <= #1 bit_addr;
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bit_select <= #1 rd_addr[2:0];
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bit_select <= #1 rd_addr[2:0];
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end
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end
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always @(posedge clk or posedge rst)
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if (rst) begin
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rd_en_r <= #1 1'b0;
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wr_data_r <= #1 8'h0;
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end else begin
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rd_en_r <= #1 rd_en;
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wr_data_r <= #1 wr_data_m;
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end
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always @(rd_addr or bit_addr)
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always @(rd_addr or bit_addr)
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casex ( {bit_addr, rd_addr[7]} ) // synopsys full_case parallel_case
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casex ( {bit_addr, rd_addr[7]} ) // synopsys full_case parallel_case
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2'b0?: rd_addr_m = rd_addr;
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2'b0?: rd_addr_m = rd_addr;
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2'b10: rd_addr_m = {4'b0010, rd_addr[6:3]};
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2'b10: rd_addr_m = {4'b0010, rd_addr[6:3]};
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2'b11: rd_addr_m = {1'b1, rd_addr[6:3], 3'b000};
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2'b11: rd_addr_m = {1'b1, rd_addr[6:3], 3'b000};
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