URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ram_top.v] - Diff between revs 4 and 41

Rev 4	Rev 41
Line 81...	Line 81...

`assign bit_data_out = rd_data[bit_select];`	`assign bit_data_out = rd_data[bit_select];`



`oc8051_ram oc8051_ram1(.clk(clk), .rd_addr(rd_addr_m), .rd_data(rd_data), .wr_addr(wr_addr_m),`	`oc8051_ram oc8051_ram1(.clk(clk), .rst(rst), .rd_addr(rd_addr_m), .rd_data(rd_data), .wr_addr(wr_addr_m),`
`.wr_data(wr_data_m), .wr(wr));`	`.wr_data(wr_data_m), .wr(wr));`


`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst) begin`	`if (rst) begin`