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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/09/30 17:33:59 simont
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// prepared header
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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Line 68... |
// bit_data_in (in) bit data input [oc8051_alu.desCy]
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// bit_data_in (in) bit data input [oc8051_alu.desCy]
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// bit_data_out (out) bit data output [oc8051_ram_sel.bit_in]
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// bit_data_out (out) bit data output [oc8051_ram_sel.bit_in]
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//
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//
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input clk, wr, bit_addr, bit_data_in, rst;
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input clk, wr, bit_addr, bit_data_in, rst;
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input [7:0] rd_addr, wr_addr, wr_data;
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input [7:0] wr_data;
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input [7:0] rd_addr, wr_addr;
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output bit_data_out;
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output bit_data_out;
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output [7:0] rd_data;
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output [7:0] rd_data;
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// rd_addr_m read address modified
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// rd_addr_m read address modified
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// wr_addr_m write address modified
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// wr_addr_m write address modified
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// wr_data_m write data modified
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// wr_data_m write data modified
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reg [7:0] rd_addr_m, wr_addr_m, wr_data_m;
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reg [7:0] wr_data_m;
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reg [7:0] rd_addr_m, wr_addr_m;
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// bit_addr_r bit addresable instruction (registerd)
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// bit_addr_r bit addresable instruction (registerd)
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reg bit_addr_r;
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reg bit_addr_r;
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reg [2:0] bit_select;
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reg [2:0] bit_select;
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Line 113... |
end
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end
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always @(wr_addr or bit_addr_r)
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always @(wr_addr or bit_addr_r)
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begin
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begin
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casex ({bit_addr_r, wr_addr[7]})
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casex ({bit_addr_r, wr_addr[7]})
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2'b10: wr_addr_m = {4'b0010, wr_addr[6:3]};
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2'b10: wr_addr_m = {8'h00, 4'b0010, wr_addr[6:3]};
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2'b11: wr_addr_m = {1'b1, wr_addr[6:3], 3'b000};
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2'b11: wr_addr_m = {8'h00, 1'b1, wr_addr[6:3], 3'b000};
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default: wr_addr_m = wr_addr;
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default: wr_addr_m = wr_addr;
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endcase
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endcase
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end
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end
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always @(rd_data or bit_select or bit_data_in or wr_data or bit_addr_r)
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always @(rd_data or bit_select or bit_data_in or wr_data or bit_addr_r)
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