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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ram_top.v] - Diff between revs 89 and 95
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Rev 95 |
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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/01/26 14:19:22 rherveille
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// Replaced oc8051_ram by generic_dpram.
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//
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// Revision 1.5 2003/01/13 14:14:41 simont
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// Revision 1.5 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.4 2002/09/30 17:33:59 simont
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// Revision 1.4 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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reg [2:0] bit_select;
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reg [2:0] bit_select;
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assign bit_data_out = rd_data[bit_select];
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assign bit_data_out = rd_data[bit_select];
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/*
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oc8051_ram oc8051_ram1(.clk(clk), .rst(rst), .rd_addr(rd_addr_m), .rd_data(rd_data), .wr_addr(wr_addr_m),
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.wr_data(wr_data_m), .wr(wr));
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*/
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generic_dpram #(ram_aw, 8) oc8051_ram1(
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oc8051_ram oc8051_ram1(.clk(clk), .rst(rst), .rd_addr(rd_addr_m), .rd_data(rd_data), .wr_addr(wr_addr_m),
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.rclk ( clk ),
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.wr_data(wr_data_m), .wr(wr));
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.rrst ( rst ),
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.rce ( 1'b1 ),
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.oe ( 1'b1 ),
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.raddr ( rd_addr_m ),
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.do ( rd_data ),
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.wclk ( clk ),
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.wrst ( rst ),
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.wce ( 1'b1 ),
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.we ( wr ),
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.waddr ( wr_addr_m ),
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.di ( wr_data_m )
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);
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/*
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generic_dpram #(ram_aw, 8) oc8051_ram1(
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.rclk ( clk ),
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.rrst ( rst ),
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.rce ( 1'b1 ),
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.oe ( 1'b1 ),
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.raddr ( rd_addr_m ),
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.do ( rd_data ),
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.wclk ( clk ),
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.wrst ( rst ),
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.wce ( 1'b1 ),
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.we ( wr ),
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.waddr ( wr_addr_m ),
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.di ( wr_data_m )
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);
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*/
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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bit_addr_r <= #1 1'b0;
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bit_addr_r <= #1 1'b0;
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bit_select <= #1 3'b0;
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bit_select <= #1 3'b0;
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