URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_rom.v] - Diff between revs 92 and 109

Rev 92	Rev 109
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2003/04/02 11:16:22 simont`
	`// initial inport`
	`//`
`// Revision 1.4 2002/10/23 17:00:18 simont`	`// Revision 1.4 2002/10/23 17:00:18 simont`
`// signal es_int=1'b0`	`// signal es_int=1'b0`
`//`	`//`
`// Revision 1.3 2002/09/30 17:34:01 simont`	`// Revision 1.3 2002/09/30 17:34:01 simont`
`// prepared header`	`// prepared header`
`//`	`//`
`//`	`//`
	`include "oc8051_defines.v"

`module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);`	`module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);`

`//parameter INT_ROM_WID= 15;`	`//parameter INT_ROM_WID= 15;`

Line 66...	Line 70...
`wire ea;`	`wire ea;`

`reg ea_int;`	`reg ea_int;`


`ifdef OC8051_XILINX_RAM	`ifdef OC8051_XILINX_ROM

`parameter INT_ROM_WID= 12;`	`parameter INT_ROM_WID= 12;`

`reg [4:0] addr01;`	`reg [4:0] addr01;`

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`endmodule`	`endmodule`


`ifdef OC8051_XILINX_RAM	`ifdef OC8051_XILINX_ROM

`//rom0`	`//rom0`
`module rom0 (o,a);`	`module rom0 (o,a);`
`input [4:0] a;`	`input [4:0] a;`
`output [7:0] o;`	`output [7:0] o;`