| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/03/28 17:45:57 simont
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// change module name.
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//
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// Revision 1.3 2003/01/21 13:51:30 simont
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// Revision 1.3 2003/01/21 13:51:30 simont
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// add include oc8051_defines.v
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// add include oc8051_defines.v
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//
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//
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// Revision 1.2 2003/01/13 14:14:41 simont
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// Revision 1.2 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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| Line 156... |
Line 159... |
wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit, pca_bit;
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wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit, pca_bit;
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wire p, int_uart, tf0, tf1, tr0, tr1;
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wire p, int_uart, tf0, tf1, tr0, tr1;
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wire dps, rclk, tclk, brate2, tc2_int;
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wire dps, rclk, tclk, brate2, tc2_int;
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wire [7:0] b_reg, psw, ports, uart, int_out, tc_out, tc2, sp_out;
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wire [7:0] b_reg, psw, ports, uart, int_out, tc_out, tc2, sp_out;
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wire pres_ow;
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assign cy = psw[7];
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assign cy = psw[7];
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assign srcAc = psw [6];
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assign srcAc = psw [6];
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| Line 233... |
Line 237... |
//
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//
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// timer/counter control
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// timer/counter control
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// TH0, TH1, TL0, TH1, TMOD
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// TH0, TH1, TL0, TH1, TMOD
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oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0),
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oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .ie0(int0), .ie1(int1), .tr0(tr0),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .ie0(int0), .ie1(int1), .tr0(tr0),
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.tr1(tr1), .t0(t0), .t1(t1), .data_out(tc_out), .tf0(tf0), .tf1(tf1));
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.tr1(tr1), .t0(t0), .t1(t1), .data_out(tc_out), .tf0(tf0), .tf1(tf1), .pres_ow(pres_ow));
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//
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//
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// timer/counter 2
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// timer/counter 2
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// TH2, TH2, RCAPL2L, RCAPL2H, T2CON, T2MOD
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// TH2, TH2, RCAPL2L, RCAPL2H, T2CON
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oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0_r), .data_in(dat1), .wr(we),
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oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0_r), .data_in(dat1), .wr(we),
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.wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex), .data_out(tc2), .bit_out(tc2_bit),
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.wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex), .data_out(tc2), .bit_out(tc2_bit),
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.rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int));
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.rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int), .pres_ow(pres_ow));
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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| Line 286... |
Line 290... |
`OC8051_SFR_TCON: dat0 = int_out;
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`OC8051_SFR_TCON: dat0 = int_out;
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`OC8051_SFR_RCAP2H: dat0 = tc2;
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`OC8051_SFR_RCAP2H: dat0 = tc2;
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`OC8051_SFR_RCAP2L: dat0 = tc2;
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`OC8051_SFR_RCAP2L: dat0 = tc2;
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`OC8051_SFR_TH2: dat0 = tc2;
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`OC8051_SFR_TH2: dat0 = tc2;
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`OC8051_SFR_TL2: dat0 = tc2;
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`OC8051_SFR_TL2: dat0 = tc2;
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`OC8051_SFR_T2MOD: dat0 = tc2;
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`OC8051_SFR_T2CON: dat0 = tc2;
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`OC8051_SFR_T2CON: dat0 = tc2;
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default: dat0 = 8'h00;
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default: dat0 = 8'h00;
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endcase
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endcase
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end
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end
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