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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_sfr.v] - Diff between revs 132 and 134
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| Rev 132 |
Rev 134 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2003/04/25 17:15:51 simont
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// change branch instruction execution (reduse needed clock periods).
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//
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// Revision 1.10 2003/04/10 12:43:19 simont
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// Revision 1.10 2003/04/10 12:43:19 simont
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// defines for pherypherals added
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// defines for pherypherals added
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//
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//
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// Revision 1.9 2003/04/09 16:24:03 simont
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// Revision 1.9 2003/04/09 16:24:03 simont
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// change wr_sft to 2 bit wire.
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// change wr_sft to 2 bit wire.
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Line 563... |
dat0 <= #1 dat1;
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dat0 <= #1 dat1;
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wait_data <= #1 1'b0;
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wait_data <= #1 1'b0;
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end else if (
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end else if (
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(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r) | //write and read same address
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(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address
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) & !wait_data) begin
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wait_data <= #1 1'b1;
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wait_data <= #1 1'b1;
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end else if ((
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end else if ((
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((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
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((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
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((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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