URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_sfr.v] - Diff between revs 134 and 139

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 134	Rev 139
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.12 2003/04/29 11:24:31 simont`
	`// fix bug in case execution of two data dependent instructions.`
	`//`
`// Revision 1.11 2003/04/25 17:15:51 simont`	`// Revision 1.11 2003/04/25 17:15:51 simont`
`// change branch instruction execution (reduse needed clock periods).`	`// change branch instruction execution (reduse needed clock periods).`
`//`	`//`
`// Revision 1.10 2003/04/10 12:43:19 simont`	`// Revision 1.10 2003/04/10 12:43:19 simont`
`// defines for pherypherals added`	`// defines for pherypherals added`
Line 87...	Line 90...


`module oc8051_sfr (rst, clk,`	`module oc8051_sfr (rst, clk,`
`adr0, adr1, dat0,`	`adr0, adr1, dat0,`
`dat1, dat2, bit_in,`	`dat1, dat2, bit_in,`
	`des_acc,`
`we, wr_bit,`	`we, wr_bit,`
`bit_out,`	`bit_out,`
`wr_sfr, acc,`	`wr_sfr, acc,`
`ram_wr_sel, ram_rd_sel,`	`ram_wr_sel, ram_rd_sel,`
`sp, sp_w,`	`sp, sp_w,`
Line 164...	Line 168...
`comp_sel;`	`comp_sel;`
`input [2:0] ram_rd_sel,`	`input [2:0] ram_rd_sel,`
`ram_wr_sel;`	`ram_wr_sel;`
`input [7:0] adr0, //address 0 input`	`input [7:0] adr0, //address 0 input`
`adr1, //address 1 input`	`adr1, //address 1 input`
	`des_acc,`
`dat1, //data 1 input (des1)`	`dat1, //data 1 input (des1)`
`dat2; //data 2 input (des2)`	`dat2; //data 2 input (des2)`

`output bit_out,`	`output bit_out,`
`intr,`	`intr,`
Line 298...	Line 303...
`// accumulator`	`// accumulator`
`// ACC`	`// ACC`
`oc8051_acc oc8051_acc1(.clk(clk),`	`oc8051_acc oc8051_acc1(.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.bit_in(bit_in),`	`.bit_in(bit_in),`
`.data_in(dat1),`	`.data_in(des_acc),`
`.data2_in(dat2),`	`.data2_in(dat2),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
`.wr_sfr(wr_sfr),`	`.wr_sfr(wr_sfr),`
`.wr_addr(adr1),`	`.wr_addr(adr1),`
Line 314...	Line 319...
`// b register`	`// b register`
`// B`	`// B`
`oc8051_b_register oc8051_b_register (.clk(clk),`	`oc8051_b_register oc8051_b_register (.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.bit_in(bit_in),`	`.bit_in(bit_in),`
`.data_in(dat1),`	`.data_in(des_acc),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
`.wr_addr(adr1),`	`.wr_addr(adr1),`
`.data_out(b_reg));`	`.data_out(b_reg));`

Line 340...	Line 345...
`//data pointer`	`//data pointer`
`// DPTR, DPH, DPL`	`// DPTR, DPH, DPL`
`oc8051_dptr oc8051_dptr1(.clk(clk),`	`oc8051_dptr oc8051_dptr1(.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.addr(adr1),`	`.addr(adr1),`
`.data_in(dat1),`	`.data_in(des_acc),`
`.data2_in(dat2),`	`.data2_in(dat2),`
`.wr(we),`	`.wr(we),`
`.wr_bit(wr_bit_r),`	`.wr_bit(wr_bit_r),`
`.data_hi(dptr_hi),`	`.data_hi(dptr_hi),`
`.data_lo(dptr_lo),`	`.data_lo(dptr_lo),`

Browse

Tools

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_sfr.v] - Diff between revs 134 and 139