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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2003/05/05 15:46:37 simont
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// add aditional alu destination to solve critical path.
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//
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// Revision 1.12 2003/04/29 11:24:31 simont
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// Revision 1.12 2003/04/29 11:24:31 simont
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// fix bug in case execution of two data dependent instructions.
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// fix bug in case execution of two data dependent instructions.
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//
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//
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// Revision 1.11 2003/04/25 17:15:51 simont
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// Revision 1.11 2003/04/25 17:15:51 simont
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// change branch instruction execution (reduse needed clock periods).
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// change branch instruction execution (reduse needed clock periods).
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| Line 563... |
Line 566... |
begin
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begin
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if (rst) begin
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if (rst) begin
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dat0 <= #1 8'h00;
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dat0 <= #1 8'h00;
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wait_data <= #1 1'b0;
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wait_data <= #1 1'b0;
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end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
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end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
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dat0 <= #1 dat1;
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dat0 <= #1 des_acc;
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wait_data <= #1 1'b0;
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wait_data <= #1 1'b0;
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end else if (
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end else if (
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(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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(
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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// ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r) | //write and read same address
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r) | //write and read same address
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(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address
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(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address
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) & !wait_data) begin
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) & !wait_data) begin
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wait_data <= #1 1'b1;
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wait_data <= #1 1'b1;
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| Line 643... |
Line 647... |
end
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end
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//
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//
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//set output in case of address (bit)
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//set output in case of address (bit)
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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bit_out <= #1 1'h0;
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bit_out <= #1 1'h0;
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else if (
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else if (
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