URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Diff between revs 112 and 116

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 112	Rev 116
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2003/04/04 10:34:13 simont`
	`// change timers to meet timing specifications (add divider with 12)`
	`//`
`// Revision 1.5 2003/01/13 14:14:41 simont`	`// Revision 1.5 2003/01/13 14:14:41 simont`
`// replace some modules`	`// replace some modules`
`//`	`//`
`// Revision 1.4 2002/09/30 17:33:59 simont`	`// Revision 1.4 2002/09/30 17:33:59 simont`
`// prepared header`	`// prepared header`
Line 59...	Line 62...
`//synopsys translate_on`	`//synopsys translate_on`



`module oc8051_tc (clk, rst,`	`module oc8051_tc (clk, rst,`
`wr_addr, rd_addr,`	`data_in,`
`data_in, data_out,`	`wr_addr,`
`wr, wr_bit,`	`wr, wr_bit,`
`ie0, ie1,`	`ie0, ie1,`
`tr0, tr1,`	`tr0, tr1,`
`t0, t1,`	`t0, t1,`
`tf0, tf1,`	`tf0, tf1,`
`pres_ow);`	`pres_ow,`
	`//registers`
	`tmod, tl0, th0, tl1, th1);`

`input [7:0] wr_addr,`	`input [7:0] wr_addr,`
`data_in,`	`data_in;`
`rd_addr;`
`input clk,`	`input clk,`
`rst,`	`rst,`
`wr,`	`wr,`
`wr_bit,`	`wr_bit,`
`ie0,`	`ie0,`
`ie1,`	`ie1,`
`tr0,`	`tr0,`
`tr1,`	`tr1,`
`t0,`	`t0,`
`t1;`	`t1;`
`output [7:0] data_out;`	`output [7:0] tmod,`
	`tl0,`
	`th0,`
	`tl1,`
	`th1;`
`output tf0,`	`output tf0,`
`tf1,`	`tf1,`
`pres_ow;`	`pres_ow;`


`reg [7:0] tmod, tl0, th0, tl1, th1, data_out;`	`reg [7:0] tmod, tl0, th0, tl1, th1;`
`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`	`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`

`reg pres_ow;`	`reg pres_ow;`
`reg [3:0] prescaler;`	`reg [3:0] prescaler;`

Line 216...	Line 224...
`end`	`end`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`always @(posedge clk or posedge rst)`
`begin`
`if (rst) data_out <= #1 8'h0;`
else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) \|
(wr_addr==`OC8051_SFR_TH1)\|(wr_addr==`OC8051_SFR_TL0)\|(wr_addr==`OC8051_SFR_TL1)\|
(wr_addr==`OC8051_SFR_TMOD))) begin
`data_out <= #1 data_in;`
`end else begin`
`case (rd_addr)`
`OC8051_SFR_TH0: data_out <= #1 th0;
`OC8051_SFR_TH1: data_out <= #1 th1;
`OC8051_SFR_TL0: data_out <= #1 tl0;
`OC8051_SFR_TL1: data_out <= #1 tl1;
`default: data_out <= #1 tmod;`
`endcase`
`end`
`end`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`begin`	`begin`
`if (rst) begin`	`if (rst) begin`
`prescaler <= #1 4'h0;`	`prescaler <= #1 4'h0;`

Browse

Tools

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Diff between revs 112 and 116