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Rev 120	Rev 179
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.8 2003/04/10 12:43:19 simont`
	`// defines for pherypherals added`
	`//`
`// Revision 1.7 2003/04/07 14:58:02 simont`	`// Revision 1.7 2003/04/07 14:58:02 simont`
`// change sfr's interface.`	`// change sfr's interface.`
`//`	`//`
`// Revision 1.6 2003/04/04 10:34:13 simont`	`// Revision 1.6 2003/04/04 10:34:13 simont`
`// change timers to meet timing specifications (add divider with 12)`	`// change timers to meet timing specifications (add divider with 12)`
Line 137...	Line 140...
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
`th0 <= #1 data_in;`	`th0 <= #1 data_in;`
`tf0 <= #1 1'b0;`	`tf0 <= #1 1'b0;`
`tf1_0 <= #1 1'b0;`	`tf1_0 <= #1 1'b0;`
`end else begin`	`end else begin`
`case (tmod[1:0])`	`case (tmod[1:0]) /* synopsys full_case parallel_case */`
`OC8051_MODE0: begin // mode 0	`OC8051_MODE0: begin // mode 0
`tf1_0 <= #1 1'b0;`	`tf1_0 <= #1 1'b0;`
`if (tc0_add)`	`if (tc0_add)`
`{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;`	`{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;`
`end`	`end`
Line 171...	Line 174...

`if (tr1 & pres_ow)`	`if (tr1 & pres_ow)`
`{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;`	`{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;`

`end`	`end`
`default:begin`	`/* default:begin`
`tf0 <= #1 1'b0;`	`tf0 <= #1 1'b0;`
`tf1_0 <= #1 1'b0;`	`tf1_0 <= #1 1'b0;`
`end`	`end*/`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`//`	`//`
Line 195...	Line 198...
`tf1_1 <= #1 1'b0;`	`tf1_1 <= #1 1'b0;`
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
`th1 <= #1 data_in;`	`th1 <= #1 data_in;`
`tf1_1 <= #1 1'b0;`	`tf1_1 <= #1 1'b0;`
`end else begin`	`end else begin`
`case (tmod[5:4])`	`case (tmod[5:4]) /* synopsys full_case parallel_case */`
`OC8051_MODE0: begin // mode 0	`OC8051_MODE0: begin // mode 0
`if (tc1_add)`	`if (tc1_add)`
`{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;`	`{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;`
`end`	`end`
`OC8051_MODE1: begin // mode 1	`OC8051_MODE1: begin // mode 1
Line 217...	Line 220...
`tl1 <=#1 tl1 + 8'h1;`	`tl1 <=#1 tl1 + 8'h1;`
`tf1_1 <= #1 1'b0;`	`tf1_1 <= #1 1'b0;`
`end`	`end`
`end`	`end`
`end`	`end`
`default:begin`	`/* default:begin`
`tf1_1 <= #1 1'b0;`	`tf1_1 <= #1 1'b0;`
`end`	`end*/`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

Line 42...

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.8  2003/04/10 12:43:19  simont

// defines for pherypherals added

//

// Revision 1.7  2003/04/07 14:58:02  simont

// Revision 1.7  2003/04/07 14:58:02  simont

// change sfr's interface.

// change sfr's interface.

//

//

// Revision 1.6  2003/04/04 10:34:13  simont

// Revision 1.6  2003/04/04 10:34:13  simont

// change timers to meet timing specifications (add divider with 12)

// change timers to meet timing specifications (add divider with 12)

Line 137...

Line 140...

 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin

 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin

   th0 <= #1 data_in;

   th0 <= #1 data_in;

   tf0 <= #1 1'b0;

   tf0 <= #1 1'b0;

   tf1_0 <= #1 1'b0;

   tf1_0 <= #1 1'b0;

 end else begin

 end else begin

     case (tmod[1:0])

     case (tmod[1:0]) /* synopsys full_case parallel_case */

      `OC8051_MODE0: begin                       // mode 0

      `OC8051_MODE0: begin                       // mode 0

        tf1_0 <= #1 1'b0;

        tf1_0 <= #1 1'b0;

        if (tc0_add)

        if (tc0_add)

          {tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;

          {tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;

end

end

Line 171...

Line 174...

         if (tr1 & pres_ow)

         if (tr1 & pres_ow)

           {tf1_0, th0} <= #1 {1'b0, th0} +1'b1;

           {tf1_0, th0} <= #1 {1'b0, th0} +1'b1;

end

end

      default:begin

/*      default:begin

        tf0 <= #1 1'b0;

        tf0 <= #1 1'b0;

        tf1_0 <= #1 1'b0;

        tf1_0 <= #1 1'b0;

end

      end*/

    endcase

    endcase

end

end

end

end

//

//

Line 195...

Line 198...

   tf1_1 <= #1 1'b0;

   tf1_1 <= #1 1'b0;

 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin

 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin

   th1 <= #1 data_in;

   th1 <= #1 data_in;

   tf1_1 <= #1 1'b0;

   tf1_1 <= #1 1'b0;

 end else begin

 end else begin

     case (tmod[5:4])

     case (tmod[5:4]) /* synopsys full_case parallel_case */

      `OC8051_MODE0: begin                       // mode 0

      `OC8051_MODE0: begin                       // mode 0

        if (tc1_add)

        if (tc1_add)

          {tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;

          {tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;

end

end

      `OC8051_MODE1: begin                       // mode 1

      `OC8051_MODE1: begin                       // mode 1

Line 217...

Line 220...

            tl1 <=#1 tl1 + 8'h1;

            tl1 <=#1 tl1 + 8'h1;

            tf1_1 <= #1 1'b0;

            tf1_1 <= #1 1'b0;

end

end

end

end

end

end

      default:begin

/*      default:begin

        tf1_1 <= #1 1'b0;

        tf1_1 <= #1 1'b0;

end

      end*/

    endcase

    endcase

end

end

end

end

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Diff between revs 120 and 179