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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/01/13 14:13:12 simont
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// initial import
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//
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//
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//
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//
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//
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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//synopsys translate_on
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//synopsys translate_on
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module oc8051_tc2 (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, bit_in, t2, t2ex, data_out, bit_out,
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module oc8051_tc2 (clk, rst,
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rclk, tclk, brate2, tc2_int);
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wr_addr, rd_addr,
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data_in, data_out, bit_out,
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input [7:0] wr_addr, data_in, rd_addr;
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wr, wr_bit, bit_in,
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input clk, rst, wr, wr_bit, t2, t2ex, bit_in;
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t2, t2ex,
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rclk, tclk,
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brate2, tc2_int,
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pres_ow);
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input [7:0] wr_addr,
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data_in,
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rd_addr;
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input clk,
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rst,
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wr,
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wr_bit,
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t2,
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t2ex,
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bit_in,
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pres_ow; //prescalre owerflov
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output [7:0] data_out;
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output [7:0] data_out;
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output tc2_int, bit_out, rclk, tclk, brate2;
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output tc2_int,
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bit_out,
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rclk,
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tclk,
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brate2;
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reg [7:0] data_out;
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reg [7:0] data_out;
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reg brate2;
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reg brate2;
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reg [7:0] t2con, t2mod, tl2, th2, rcap2l, rcap2h;
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reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;
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reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;
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reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;
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wire run;
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wire run;
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wire dcen;
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assign dcen = t2mod[0];
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//
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//
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// t2con
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// t2con
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wire tf2, exf2, exen2, tr2, ct2, cprl2;
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wire tf2, exf2, exen2, tr2, ct2, cprl2;
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assign tc2_int = tf2 | exf2;
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assign tc2_int = tf2 | exf2;
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t2con <= #1 data_in;
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t2con <= #1 data_in;
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
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t2con[wr_addr[2:0]] <= #1 bit_in;
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t2con[wr_addr[2:0]] <= #1 bit_in;
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end else if (tf2_set) begin
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end else if (tf2_set) begin
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t2con[7] <= #1 1'b1;
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t2con[7] <= #1 1'b1;
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//auto reload mode, dcen=1 : toggle exf2;
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end else if (exen2 & neg_trans) begin
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if (!(rclk | tclk) & !cprl2 & dcen)
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t2con[6] <= #1 1'b1;
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t2con[6] <= #1 !t2con[6];
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end else if (exen2 & (rclk | tclk | cprl2 | !dcen) & neg_trans) begin
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t2con <= #1 {t2con[7], 1'b1, t2con[5:0]};
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end
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end
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end
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end
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//
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//
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// t2mod
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always @(posedge clk or posedge rst)
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begin
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if (rst) begin
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t2mod <= #1 `OC8051_RST_T2MOD;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2MOD)) begin
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t2mod <= #1 data_in;
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end
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end
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//
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//th2, tl2
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//th2, tl2
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assign run = tr2 & (!ct2 | (ct2 & tc2_event));
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assign run = tr2 & ((!ct2 & pres_ow) | (ct2 & tc2_event));
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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//
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//
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Line 148... |
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
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//
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//
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// write to timer 2 low
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// write to timer 2 low
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//
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//
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tl2 <= #1 data_in;
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tl2 <= #1 data_in;
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end else if (!(rclk | tclk) & !cprl2 & exen2 & !dcen) begin
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end else if (!(rclk | tclk) & !cprl2 & exen2 & neg_trans) begin
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//
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//
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// avto reload mode, exen2=1, 0-1 transition on t2ex pin
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// avto reload mode, exen2=1, 0-1 transition on t2ex pin
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//
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//
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th2 <= #1 rcap2h;
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th2 <= #1 rcap2h;
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tl2 <= #1 rcap2l;
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tl2 <= #1 rcap2l;
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Line 173... |
end else if (cprl2) begin
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end else if (cprl2) begin
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//
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//
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// capture mode
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// capture mode
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//
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//
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{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
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{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
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end else if (!dcen | t2ex) begin
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end else begin
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//
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//
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// auto reload mode, up counter
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// auto reload mode
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//
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//
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if (&{th2, tl2}) begin
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if (&{th2, tl2}) begin
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th2 <= #1 rcap2h;
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th2 <= #1 rcap2h;
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tl2 <= #1 rcap2l;
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tl2 <= #1 rcap2l;
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tf2_set <= #1 1'b1;
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tf2_set <= #1 1'b1;
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end else begin
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end else begin
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{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
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{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
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end
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end
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end else begin
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//
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// auto reload mode, down counter
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//
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if ({th2, tl2}=={rcap2h, rcap2l}) begin
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th2 <= #1 8'hff;
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tl2 <= #1 8'hff;
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tf2_set <= #1 1'b1;
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end else begin
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{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} - 17'h1;
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end
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end
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end
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end else tf2_set <= #1 1'b0;
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end else tf2_set <= #1 1'b0;
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end
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end
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end else begin
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end else begin
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tc2_event <= #1 1'b0;
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tc2_event <= #1 1'b0;
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end
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end
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end
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end
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always @(rd_addr or t2con or t2mod or tl2 or th2 or rcap2l or rcap2h)
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always @(rd_addr or t2con or tl2 or th2 or rcap2l or rcap2h)
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begin
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begin
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case (rd_addr)
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case (rd_addr)
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`OC8051_SFR_RCAP2H: data_out = rcap2h;
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`OC8051_SFR_RCAP2H: data_out = rcap2h;
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`OC8051_SFR_RCAP2L: data_out = rcap2l;
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`OC8051_SFR_RCAP2L: data_out = rcap2l;
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`OC8051_SFR_TH2: data_out = th2;
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`OC8051_SFR_TH2: data_out = th2;
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`OC8051_SFR_TL2: data_out = tl2;
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`OC8051_SFR_TL2: data_out = tl2;
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`OC8051_SFR_T2MOD: data_out = t2mod;
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default: data_out = t2con;
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default: data_out = t2con;
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endcase
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endcase
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end
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end
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