| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.18 2003/01/13 14:14:41 simont
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// replace some modules
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//
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// Revision 1.17 2002/11/05 17:23:54 simont
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// Revision 1.17 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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// add module oc8051_sfr, 256 bytes internal ram
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//
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//
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// Revision 1.16 2002/10/28 14:55:00 simont
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// Revision 1.16 2002/10/28 14:55:00 simont
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// fix bug in interface to external data ram
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// fix bug in interface to external data ram
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| Line 64... |
Line 67... |
// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_top (rst_i, clk, int0, int1, ea, iadr_o, idat_i,istb_o, iack_i, ddat_i,
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module oc8051_top (wb_rst_i, wb_clk_i,
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icyc_o, ddat_o, dadr_o, dwe_o, dack_i, dstb_o, dcyc_o, p0_in, p1_in, p2_in, p3_in, p0_out,
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//interface to instruction rom
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p1_out, p2_out, p3_out, rxd, txd, t0, t1, t2, t2ex);
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wbi_adr_o, wbi_dat_i, wbi_stb_o, wbi_ack_i, wbi_cyc_o, wbi_err_i,
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//
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//interface to data ram
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// rst_i (in) reset - pin
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wbd_dat_i, wbd_dat_o,
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// clk (in) clock - pin
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wbd_adr_o, wbd_we_o, wbd_ack_i, wbd_stb_o, wbd_cyc_o, wbd_err_i,
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// iadr_o (out) program rom addres (pin + internal)
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// interrupt interface
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// int0 (in) external interrupt 0
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int0_i, int1_i,
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// int1 (in) external interrupt 1
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// external access (active low)
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// dat_i (in) exteranal ram input
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ea_in,
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// dat_o (out) exteranal ram output
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// port interface
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// adr_o (out) external address
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p0_i, p1_i, p2_i, p3_i,
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// dwe_o (out) write to external ram
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p0_o, p1_o, p2_o, p3_o,
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// dstb_o
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// serial interface
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// ack_i
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rxd_i, txd_o,
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// idat_i (in) data from external program rom
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// counter interface
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// istb_o (out) strobe to program rom
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t0_i, t1_i, t2_i, t2ex_i);
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// iack_i (in) acknowlage from external rom
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// icyc_o (out)
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// p0_in, p1_in, p2_in, p3_in (in) port inputs
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// p0_out, p1_out, p2_out, p3_out (out) port outputs
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// rxd (in) receive
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// txd (out) transmit
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// t0, t1 (in) t/c external inputs
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//
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//
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input rst_i, clk, int0, int1, ea, rxd, t0, t1, dack_i, iack_i, t2, t2ex;
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input wb_rst_i, // reset input
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input [7:0] ddat_i, p0_in, p1_in, p2_in, p3_in;
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wb_clk_i, // clock input
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input [31:0] idat_i;
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int0_i, // interrupt 0
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int1_i, // interrupt 1
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ea_in, // external access
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rxd_i, // receive
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t0_i, // counter 0 input
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t1_i, // counter 1 input
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wbd_ack_i, // data acknowalge
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wbi_ack_i, // instruction acknowlage
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wbd_err_i, // data error
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wbi_err_i, // instruction error
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t2_i, // counter 2 input
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t2ex_i; // ???
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input [7:0] wbd_dat_i, // ram data input
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p0_i, // port 0 input
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p1_i, // port 1 input
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p2_i, // port 2 input
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p3_i; // port 3 input
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input [31:0] wbi_dat_i; // rom data input
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output wbd_we_o, // data write enable
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txd_o, // transnmit
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wbd_stb_o, // data strobe
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wbd_cyc_o, // data cycle
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wbi_stb_o, // instruction strobe
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wbi_cyc_o; // instruction cycle
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output [7:0] wbd_dat_o, // data output
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p0_o, // port 0 output
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p1_o, // port 1 output
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p2_o, // port 2 output
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p3_o; // port 3 output
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output dwe_o, txd, dstb_o, dcyc_o, istb_o, icyc_o;
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output [15:0] wbd_adr_o, // data address
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output [7:0] ddat_o, p0_out, p1_out, p2_out, p3_out;
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wbi_adr_o; // instruction address
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output [15:0] dadr_o, iadr_o;
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wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, rn_mem, data_out;
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wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, rn_mem, data_out;
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wire [7:0] op1, op2, op3;
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wire [7:0] op1, op2, op3;
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wire [7:0] acc, p0_out, p1_out, p2_out, p3_out;
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wire [7:0] acc, p0_out, p1_out, p2_out, p3_out;
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wire [7:0] sp, sp_w;
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wire [7:0] sp, sp_w;
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wire [15:0] pc;
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wire [15:0] pc;
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wire rst;
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assign wbd_cyc_o = wbd_stb_o;
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assign rst = rst_i;
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assign wbi_cyc_o = wbi_stb_o;
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assign dcyc_o = dstb_o;
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assign icyc_o = istb_o;
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//
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//
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// ram_rd_sel ram read (internal)
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// ram_rd_sel ram read (internal)
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// ram_wr_sel ram write (internal)
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// ram_wr_sel ram write (internal)
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// src_sel1, src_sel2 from decoder to register
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// src_sel1, src_sel2 from decoder to register
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| Line 206... |
Line 227... |
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//
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//
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// decoder
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// decoder
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oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n), .op1_c(op1_cur),
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oc8051_decoder oc8051_decoder1(.clk(wb_clk_i), .rst(wb_rst_i), .op_in(op1_n), .op1_c(op1_cur),
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.ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr),
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.ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr),
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.src_sel1(src_sel1), .src_sel2(src_sel2),
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.src_sel1(src_sel1), .src_sel2(src_sel2),
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.src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
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.src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
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.cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr),
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.cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr),
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.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
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.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
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| Line 218... |
Line 239... |
.istb(istb), .mem_act(mem_act), .mem_wait(mem_wait));
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.istb(istb), .mem_act(mem_act), .mem_wait(mem_wait));
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//
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//
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//alu
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//alu
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oc8051_alu oc8051_alu1(.rst(rst), .clk(clk), .op_code(alu_op), .rd(rd),
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oc8051_alu oc8051_alu1(.rst(wb_rst_i), .clk(wb_clk_i), .op_code(alu_op), .rd(rd),
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.src1(src1), .src2(src2), .src3(src3), .srcCy(alu_cy), .srcAc(srcAc),
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.src1(src1), .src2(src2), .src3(src3), .srcCy(alu_cy), .srcAc(srcAc),
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.des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
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.des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
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.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
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.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
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//
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//
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//data ram
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//data ram
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oc8051_ram_top oc8051_ram_top1(.clk(clk), .rst(rst), .rd_addr(rd_addr), .rd_data(ram_data),
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oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i), .rst(wb_rst_i), .rd_addr(rd_addr), .rd_data(ram_data),
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.wr_addr(wr_addr), .bit_addr(bit_addr_o), .wr_data(wr_dat), .wr(wr_o && (!wr_addr[7] || wr_ind)),
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.wr_addr(wr_addr), .bit_addr(bit_addr_o), .wr_data(wr_dat), .wr(wr_o && (!wr_addr[7] || wr_ind)),
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.bit_data_in(desCy), .bit_data_out(bit_data));
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.bit_data_in(desCy), .bit_data_out(bit_data));
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//
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//
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oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(clk), .rst(rst), .rd(rd),
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oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i), .rst(wb_rst_i), .rd(rd),
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.sel1(src_sel1), .sel2(src_sel2), .sel3(src_sel3),
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.sel1(src_sel1), .sel2(src_sel2), .sel3(src_sel3),
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.acc(acc), .ram(ram_out), .pc(pc), .dptr({dptr_hi, dptr_lo}),
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.acc(acc), .ram(ram_out), .pc(pc), .dptr({dptr_hi, dptr_lo}),
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.op1(op1_n), .op2(op2_n), .op3(op3_n),
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.op1(op1_n), .op2(op2_n), .op3(op3_n),
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.src1(src1), .src2(src2), .src3(src3));
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.src1(src1), .src2(src2), .src3(src3));
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| Line 245... |
Line 266... |
oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
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oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
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//
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//
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//program rom
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//program rom
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oc8051_rom oc8051_rom1(.rst(rst), .clk(clk), .ea_int(ea_int), .addr(iadr_o),
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oc8051_rom oc8051_rom1(.rst(wb_rst_i), .clk(wb_clk_i), .ea_int(ea_int), .addr(wbi_adr_o),
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.data1(op1_i), .data2(op2_i), .data3(op3_i));
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.data1(op1_i), .data2(op2_i), .data3(op3_i));
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//
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//
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//
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//
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oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel), .cy_in(cy), .data_in(bit_out),
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oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel), .cy_in(cy), .data_in(bit_out),
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.data_out(alu_cy));
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.data_out(alu_cy));
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//
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//
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//
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//
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oc8051_indi_addr oc8051_indi_addr1 (.clk(clk), .rst(rst), .rd_addr(rd_addr), .wr_addr(wr_addr),
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oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i), .rst(wb_rst_i), .rd_addr(rd_addr), .wr_addr(wr_addr),
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.data_in(wr_dat), .wr(wr_o), .wr_bit(bit_addr_o), .rn_out(rn_mem),
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.data_in(wr_dat), .wr(wr_o), .wr_bit(bit_addr_o), .rn_out(rn_mem),
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.ri_out(ri), .sel(op1_cur), .bank(bank_sel));
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.ri_out(ri), .sel(op1_cur), .bank(bank_sel));
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//
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//
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//
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//
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oc8051_memory_interface oc8051_memory_interface1(.clk(clk), .rst(rst),
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oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i), .rst(wb_rst_i),
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.wr_i(wr), .wr_o(wr_o), .wr_bit_i(bit_addr), .wr_bit_o(bit_addr_o), .wr_dat(wr_dat),
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.wr_i(wr), .wr_o(wr_o), .wr_bit_i(bit_addr), .wr_bit_o(bit_addr_o), .wr_dat(wr_dat),
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//rom_addr_sel
|
//rom_addr_sel
|
.iack_i(iack_i), .des1(des1), .des2(des2),
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.iack_i(wbi_ack_i), .des1(des1), .des2(des2),
|
.iadr_o(iadr_o), .sp_w(sp_w),
|
.iadr_o(wbi_adr_o), .sp_w(sp_w),
|
|
|
//ext_addr_sel
|
//ext_addr_sel
|
.dptr({dptr_hi, dptr_lo}), .ri(ri), .rn_mem(rn_mem), .dadr_o(dadr_o), .ddat_o(ddat_o),
|
.dptr({dptr_hi, dptr_lo}), .ri(ri), .rn_mem(rn_mem), .dadr_o(wbd_adr_o), .ddat_o(wbd_dat_o),
|
.dwe_o(dwe_o), .dstb_o(dstb_o), .ddat_i(ddat_i), .acc(acc), .dack_i(dack_i),
|
.dwe_o(wbd_we_o), .dstb_o(wbd_stb_o), .ddat_i(wbd_dat_i), .acc(acc), .dack_i(wbd_ack_i),
|
|
|
//ram_addr_sel
|
//ram_addr_sel
|
.rd_sel(ram_rd_sel), .wr_sel(ram_wr_sel), .sp(sp), .rn({bank_sel, op1_n[2:0]}),
|
.rd_sel(ram_rd_sel), .wr_sel(ram_wr_sel), .sp(sp), .rn({bank_sel, op1_n[2:0]}),
|
.rd_addr(rd_addr), .wr_addr(wr_addr), .rd_ind(rd_ind), .wr_ind(wr_ind),
|
.rd_addr(rd_addr), .wr_addr(wr_addr), .rd_ind(rd_ind), .wr_ind(wr_ind),
|
|
|
//op_select
|
//op_select
|
.ea(ea), .ea_int(ea_int),
|
.ea(ea_in), .ea_int(ea_int),
|
.op1_i(op1_i), .op2_i(op2_i), .op3_i(op3_i),
|
.op1_i(op1_i), .op2_i(op2_i), .op3_i(op3_i),
|
.idat_i(idat_i),
|
.idat_i(wbi_dat_i),
|
.op1_out(op1_n), .op2_out(op2_n), .op3_out(op3_n),
|
.op1_out(op1_n), .op2_out(op2_n), .op3_out(op3_n),
|
.intr(intr), .int_v(int_src), .rd(rd), .int_ack(int_ack), .istb(istb),
|
.intr(intr), .int_v(int_src), .rd(rd), .int_ack(int_ack), .istb(istb),
|
.istb_o(istb_o),
|
.istb_o(wbi_stb_o),
|
|
|
//pc
|
//pc
|
.pc_wr_sel(pc_wr_sel), .pc_wr(pc_wr), .pc(pc),
|
.pc_wr_sel(pc_wr_sel), .pc_wr(pc_wr), .pc(pc),
|
.mem_act(mem_act), .mem_wait(mem_wait),
|
.mem_act(mem_act), .mem_wait(mem_wait),
|
.bit_in(bit_data), .in_ram(ram_data),
|
.bit_in(bit_data), .in_ram(ram_data),
|
| Line 294... |
Line 315... |
|
|
|
|
//
|
//
|
//
|
//
|
|
|
oc8051_sfr oc8051_sfr1(.rst(rst), .clk(clk), .adr0(rd_addr[7:0]), .adr1(wr_addr[7:0]),
|
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i), .clk(wb_clk_i), .adr0(rd_addr[7:0]), .adr1(wr_addr[7:0]),
|
.dat0(sfr_out), .dat1(wr_dat), .dat2(des2), .we(wr_o && !wr_ind), .bit_in(desCy),
|
.dat0(sfr_out), .dat1(wr_dat), .dat2(des2), .we(wr_o && !wr_ind), .bit_in(desCy),
|
.bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .wr_sfr(wr_sfr),
|
.bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .wr_sfr(wr_sfr),
|
// acc
|
// acc
|
.acc(acc),
|
.acc(acc),
|
// sp
|
// sp
|
.sp(sp), .sp_w(sp_w),
|
.sp(sp), .sp_w(sp_w),
|
// psw
|
// psw
|
.bank_sel(bank_sel), .desAc(desAc), .desOv(desOv), .psw_set(psw_set),
|
.bank_sel(bank_sel), .desAc(desAc), .desOv(desOv), .psw_set(psw_set),
|
.srcAc(srcAc), .cy(cy),
|
.srcAc(srcAc), .cy(cy),
|
// ports
|
// ports
|
.rmw(rmw), .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
|
.rmw(rmw), .p0_out(p0_o), .p1_out(p1_o), .p2_out(p2_o), .p3_out(p3_o),
|
.p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in),
|
.p0_in(p0_i), .p1_in(p1_i), .p2_in(p2_i), .p3_in(p3_i),
|
// uart
|
// uart
|
.rxd(rxd), .txd(txd),
|
.rxd(rxd_i), .txd(txd_o),
|
// int
|
// int
|
.int_ack(int_ack), .intr(intr), .int0(int0), .int1(int1), .reti(reti), .int_src(int_src),
|
.int_ack(int_ack), .intr(intr), .int0(int0_i), .int1(int1_i),
|
|
.reti(reti), .int_src(int_src),
|
// t/c
|
// t/c
|
.t0(t0), .t1(t1), .t2(t2), .t2ex(t2ex),
|
.t0(t0_i), .t1(t1_i), .t2(t2_i), .t2ex(t2ex_i),
|
// dptr
|
// dptr
|
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo));
|
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo));
|
|
|
|
|
endmodule
|
endmodule
|
