| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.19 2003/04/02 15:08:30 simont
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// raname signals.
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//
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// Revision 1.18 2003/01/13 14:14:41 simont
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// Revision 1.18 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.17 2002/11/05 17:23:54 simont
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// Revision 1.17 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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// add module oc8051_sfr, 256 bytes internal ram
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| Line 134... |
Line 137... |
wire [7:0] sp, sp_w;
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wire [7:0] sp, sp_w;
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wire [15:0] pc;
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wire [15:0] pc;
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assign wbd_cyc_o = wbd_stb_o;
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assign wbd_cyc_o = wbd_stb_o;
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assign wbi_cyc_o = wbi_stb_o;
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//assign wbi_cyc_o = wbi_stb_o;
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//
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//
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// ram_rd_sel ram read (internal)
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// ram_rd_sel ram read (internal)
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// ram_wr_sel ram write (internal)
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// ram_wr_sel ram write (internal)
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// src_sel1, src_sel2 from decoder to register
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// src_sel1, src_sel2 from decoder to register
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| Line 222... |
Line 225... |
// bit_data bit data from ram to ram_select
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// bit_data bit data from ram to ram_select
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// bit_out bit data from ram_select to alu and cy_select
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// bit_out bit data from ram_select to alu and cy_select
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wire bit_addr, bit_data, bit_out, bit_addr_o;
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wire bit_addr, bit_data, bit_out, bit_addr_o;
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//
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//
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// cpu to cache/wb_interface
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wire iack_i,
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istb_o,
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icyc_o;
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wire [31:0] idat_i;
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wire [15:0] iadr_o;
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//
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//
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// decoder
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// decoder
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| Line 266... |
Line 275... |
oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
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oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
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//
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//
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//program rom
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//program rom
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oc8051_rom oc8051_rom1(.rst(wb_rst_i), .clk(wb_clk_i), .ea_int(ea_int), .addr(wbi_adr_o),
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oc8051_rom oc8051_rom1(.rst(wb_rst_i), .clk(wb_clk_i), .ea_int(ea_int), .addr(iadr_o),
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.data1(op1_i), .data2(op2_i), .data3(op3_i));
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.data1(op1_i), .data2(op2_i), .data3(op3_i));
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//
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//
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//
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//
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oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel), .cy_in(cy), .data_in(bit_out),
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oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel), .cy_in(cy), .data_in(bit_out),
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| Line 280... |
Line 289... |
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i), .rst(wb_rst_i), .rd_addr(rd_addr), .wr_addr(wr_addr),
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oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i), .rst(wb_rst_i), .rd_addr(rd_addr), .wr_addr(wr_addr),
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.data_in(wr_dat), .wr(wr_o), .wr_bit(bit_addr_o), .rn_out(rn_mem),
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.data_in(wr_dat), .wr(wr_o), .wr_bit(bit_addr_o), .rn_out(rn_mem),
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.ri_out(ri), .sel(op1_cur), .bank(bank_sel));
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.ri_out(ri), .sel(op1_cur), .bank(bank_sel));
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assign icyc_o = istb_o;
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//
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//
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//
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//
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oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i), .rst(wb_rst_i),
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oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i), .rst(wb_rst_i),
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// internal ram
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.wr_i(wr), .wr_o(wr_o), .wr_bit_i(bit_addr), .wr_bit_o(bit_addr_o), .wr_dat(wr_dat),
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.wr_i(wr), .wr_o(wr_o), .wr_bit_i(bit_addr), .wr_bit_o(bit_addr_o), .wr_dat(wr_dat),
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//rom_addr_sel
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.des1(des1), .des2(des2),
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.iack_i(wbi_ack_i), .des1(des1), .des2(des2),
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.rd_addr(rd_addr), .wr_addr(wr_addr),
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.iadr_o(wbi_adr_o), .sp_w(sp_w),
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.wr_ind(wr_ind),
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.bit_in(bit_data), .in_ram(ram_data),
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//ext_addr_sel
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.sfr(sfr_out), .sfr_bit(sfr_bit), .bit_out(bit_out), .iram_out(ram_out),
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.dptr({dptr_hi, dptr_lo}), .ri(ri), .rn_mem(rn_mem), .dadr_o(wbd_adr_o), .ddat_o(wbd_dat_o),
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.dwe_o(wbd_we_o), .dstb_o(wbd_stb_o), .ddat_i(wbd_dat_i), .acc(acc), .dack_i(wbd_ack_i),
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//ram_addr_sel
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.rd_sel(ram_rd_sel), .wr_sel(ram_wr_sel), .sp(sp), .rn({bank_sel, op1_n[2:0]}),
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.rd_addr(rd_addr), .wr_addr(wr_addr), .rd_ind(rd_ind), .wr_ind(wr_ind),
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//op_select
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// external instrauction rom
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.ea(ea_in), .ea_int(ea_int),
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.iack_i(iack_i),
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.iadr_o(iadr_o),
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.idat_i(idat_i),
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.istb_o(istb_o),
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// internal instruction rom
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.op1_i(op1_i), .op2_i(op2_i), .op3_i(op3_i),
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.op1_i(op1_i), .op2_i(op2_i), .op3_i(op3_i),
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.idat_i(wbi_dat_i),
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// data memory
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.dadr_o(wbd_adr_o), .ddat_o(wbd_dat_o),
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.dwe_o(wbd_we_o), .dstb_o(wbd_stb_o),
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.ddat_i(wbd_dat_i), .dack_i(wbd_ack_i),
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// from decoder
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.rd_sel(ram_rd_sel), .wr_sel(ram_wr_sel), .rn({bank_sel, op1_n[2:0]}),
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.rd_ind(rd_ind), .rd(rd),
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.mem_act(mem_act), .mem_wait(mem_wait),
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// external access
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.ea(ea_in), .ea_int(ea_int),
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// instructions outputs to cpu
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.op1_out(op1_n), .op2_out(op2_n), .op3_out(op3_n),
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.op1_out(op1_n), .op2_out(op2_n), .op3_out(op3_n),
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.intr(intr), .int_v(int_src), .rd(rd), .int_ack(int_ack), .istb(istb),
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.istb_o(wbi_stb_o),
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// interrupt interface
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.intr(intr), .int_v(int_src), .int_ack(int_ack), .istb(istb),
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.reti(reti),
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//pc
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//pc
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.pc_wr_sel(pc_wr_sel), .pc_wr(pc_wr), .pc(pc),
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.pc_wr_sel(pc_wr_sel), .pc_wr(pc_wr), .pc(pc),
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.mem_act(mem_act), .mem_wait(mem_wait),
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.bit_in(bit_data), .in_ram(ram_data),
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// sfr's
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.sfr(sfr_out), .sfr_bit(sfr_bit), .bit_out(bit_out), .iram_out(ram_out),
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.sp_w(sp_w), .dptr({dptr_hi, dptr_lo}),
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.reti(reti));
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.ri(ri), .rn_mem(rn_mem),
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.acc(acc), .sp(sp)
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);
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//
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//
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//
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//
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| Line 339... |
Line 368... |
.t0(t0_i), .t1(t1_i), .t2(t2_i), .t2ex(t2ex_i),
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.t0(t0_i), .t1(t1_i), .t2(t2_i), .t2ex(t2ex_i),
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// dptr
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// dptr
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.dptr_hi(dptr_hi), .dptr_lo(dptr_lo));
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.dptr_hi(dptr_hi), .dptr_lo(dptr_lo));
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`ifdef OC8051_CACHE
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oc8051_icache oc8051_icache1(.rst(wb_rst_i), .clk(wb_clk_i),
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// cpu
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.adr_i(iadr_o),
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.dat_o(idat_i),
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.stb_i(istb_o),
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.ack_o(iack_i),
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.cyc_i(icyc_o),
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// pins
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.dat_i(wbi_dat_i),
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.stb_o(wbi_stb_o),
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.adr_o(wbi_adr_o),
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.ack_i(wbi_ack_i),
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.cyc_o(wbi_cyc_o));
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defparam oc8051_icache1.ADR_WIDTH = 7; // cache address wihth
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defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
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defparam oc8051_icache1.BL_NUM = 31; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
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defparam oc8051_icache1.CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH)
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//
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// no cache
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//
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`else
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oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
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// cpu
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.adr_i(iadr_o),
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.dat_o(idat_i),
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.stb_i(istb_o),
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.ack_o(iack_i),
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.cyc_i(icyc_o),
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// external rom
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.dat_i(wbi_dat_i),
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.stb_o(wbi_stb_o),
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.adr_o(wbi_adr_o),
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.ack_i(wbi_ack_i),
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.cyc_o(wbi_cyc_o));
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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