| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.20 2003/04/03 19:13:28 simont
|
|
// Include instruction cache.
|
|
//
|
// Revision 1.19 2003/04/02 15:08:30 simont
|
// Revision 1.19 2003/04/02 15:08:30 simont
|
// raname signals.
|
// raname signals.
|
//
|
//
|
// Revision 1.18 2003/01/13 14:14:41 simont
|
// Revision 1.18 2003/01/13 14:14:41 simont
|
// replace some modules
|
// replace some modules
|
| Line 231... |
Line 234... |
wire iack_i,
|
wire iack_i,
|
istb_o,
|
istb_o,
|
icyc_o;
|
icyc_o;
|
wire [31:0] idat_i;
|
wire [31:0] idat_i;
|
wire [15:0] iadr_o;
|
wire [15:0] iadr_o;
|
|
wire wait_data;
|
|
|
|
|
//
|
//
|
// decoder
|
// decoder
|
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i), .rst(wb_rst_i), .op_in(op1_n), .op1_c(op1_cur),
|
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i), .rst(wb_rst_i), .op_in(op1_n), .op1_c(op1_cur),
|
.ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr),
|
.ram_rd_sel_o(ram_rd_sel), .ram_wr_sel_o(ram_wr_sel), .bit_addr(bit_addr),
|
.src_sel1(src_sel1), .src_sel2(src_sel2),
|
.src_sel1(src_sel1), .src_sel2(src_sel2),
|
.src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
|
.src_sel3(src_sel3), .alu_op_o(alu_op), .psw_set(psw_set),
|
.cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr),
|
.cy_sel(cy_sel), .wr_o(wr), .pc_wr(pc_wr),
|
.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
|
.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
|
.wr_sfr(wr_sfr), .rd(rd), .rmw(rmw),
|
.wr_sfr_o(wr_sfr), .rd(rd), .rmw(rmw),
|
.istb(istb), .mem_act(mem_act), .mem_wait(mem_wait));
|
.istb(istb), .mem_act(mem_act), .mem_wait(mem_wait),
|
|
.wait_data(wait_data));
|
|
|
|
|
//
|
//
|
//alu
|
//alu
|
oc8051_alu oc8051_alu1(.rst(wb_rst_i), .clk(wb_clk_i), .op_code(alu_op), .rd(rd),
|
oc8051_alu oc8051_alu1(.rst(wb_rst_i), .clk(wb_clk_i), .op_code(alu_op), .rd(rd),
|
| Line 365... |
Line 369... |
.int_ack(int_ack), .intr(intr), .int0(int0_i), .int1(int1_i),
|
.int_ack(int_ack), .intr(intr), .int0(int0_i), .int1(int1_i),
|
.reti(reti), .int_src(int_src),
|
.reti(reti), .int_src(int_src),
|
// t/c
|
// t/c
|
.t0(t0_i), .t1(t1_i), .t2(t2_i), .t2ex(t2ex_i),
|
.t0(t0_i), .t1(t1_i), .t2(t2_i), .t2ex(t2ex_i),
|
// dptr
|
// dptr
|
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo));
|
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo),
|
|
.wait_data(wait_data));
|
|
|
|
|
|
|
|
|
`ifdef OC8051_CACHE
|
`ifdef OC8051_CACHE
|
