| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.21 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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//
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// Revision 1.20 2003/04/03 19:13:28 simont
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// Revision 1.20 2003/04/03 19:13:28 simont
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// Include instruction cache.
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// Include instruction cache.
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//
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//
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// Revision 1.19 2003/04/02 15:08:30 simont
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// Revision 1.19 2003/04/02 15:08:30 simont
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// raname signals.
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// raname signals.
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| Line 147... |
Line 150... |
//
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//
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// ram_rd_sel ram read (internal)
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// ram_rd_sel ram read (internal)
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// ram_wr_sel ram write (internal)
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// ram_wr_sel ram write (internal)
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// src_sel1, src_sel2 from decoder to register
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// src_sel1, src_sel2 from decoder to register
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wire src_sel3;
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wire src_sel3;
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wire [2:0] ram_rd_sel, ram_wr_sel, wr_sfr;
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wire [1:0] wr_sfr;
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wire [2:0] ram_rd_sel, ram_wr_sel;
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wire [2:0] src_sel2, src_sel1;
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wire [2:0] src_sel2, src_sel1;
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//
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//
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// wr_addr ram write addres
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// wr_addr ram write addres
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// ram_out data from ram
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// ram_out data from ram
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| Line 350... |
Line 354... |
//
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//
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//
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//
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oc8051_sfr oc8051_sfr1(.rst(wb_rst_i), .clk(wb_clk_i), .adr0(rd_addr[7:0]), .adr1(wr_addr[7:0]),
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oc8051_sfr oc8051_sfr1(.rst(wb_rst_i), .clk(wb_clk_i), .adr0(rd_addr[7:0]), .adr1(wr_addr[7:0]),
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.dat0(sfr_out), .dat1(wr_dat), .dat2(des2), .we(wr_o && !wr_ind), .bit_in(desCy),
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.dat0(sfr_out), .dat1(wr_dat), .dat2(des2), .we(wr_o && !wr_ind), .bit_in(desCy),
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.bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .wr_sfr(wr_sfr),
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.bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
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.wr_sfr(wr_sfr),
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// acc
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// acc
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.acc(acc),
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.acc(acc),
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// sp
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// sp
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.sp(sp), .sp_w(sp_w),
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.sp(sp), .sp_w(sp_w),
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// psw
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// psw
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